main.map.rpt

一些很好的FPGA设计实例

Info: Found 1 design units, including 1 entities, in source file hour_counter.v
    Info: Found entity 1: hour_counter
Info: Found 1 design units, including 1 entities, in source file maincontrol.v
    Info: Found entity 1: maincontrol
Info: Found 1 design units, including 1 entities, in source file minute_counter.v
    Info: Found entity 1: minute_counter
Info: Found 1 design units, including 1 entities, in source file second_counter.v
    Info: Found entity 1: second_counter
Info: Found 1 design units, including 1 entities, in source file setdate.v
    Info: Found entity 1: setdate
Info: Found 1 design units, including 1 entities, in source file stopwatch.v
    Info: Found entity 1: stopwatch
Info: Found 1 design units, including 1 entities, in source file time_auto_and_set.bdf
    Info: Found entity 1: time_auto_and_set
Info: Found 1 design units, including 1 entities, in source file time_disp_select.v
    Info: Found entity 1: time_disp_select
Info: Found 1 design units, including 1 entities, in source file time_mux.v
    Info: Found entity 1: time_mux
Info: Found 1 design units, including 1 entities, in source file timepiece_main.bdf
    Info: Found entity 1: timepiece_main
Info: Found 1 design units, including 1 entities, in source file timeset.v
    Info: Found entity 1: timeset
Info: Found 1 design units, including 1 entities, in source file main.bdf
    Info: Found entity 1: main
Info: Elaborating entity "main" for the top level hierarchy
Info: Elaborating entity "alarmclock" for hierarchy "alarmclock:inst11"
Info: Elaborating entity "maincontrol" for hierarchy "maincontrol:inst3"
Info: Elaborating entity "fdiv" for hierarchy "fdiv:inst5"
Info: Elaborating entity "time_auto_and_set" for hierarchy "time_auto_and_set:inst1"
Info: Elaborating entity "timepiece_main" for hierarchy "time_auto_and_set:inst1|timepiece_main:inst1"
Info: Elaborating entity "hour_counter" for hierarchy "time_auto_and_set:inst1|timepiece_main:inst1|hour_counter:inst"
Info: Elaborating entity "minute_counter" for hierarchy "time_auto_and_set:inst1|timepiece_main:inst1|minute_counter:inst1"
Info: Elaborating entity "second_counter" for hierarchy "time_auto_and_set:inst1|timepiece_main:inst1|second_counter:inst2"
Info: Elaborating entity "time_mux" for hierarchy "time_auto_and_set:inst1|time_mux:inst"
Info: Elaborating entity "timeset" for hierarchy "time_auto_and_set:inst1|timeset:inst2"
Warning (10101): Verilog HDL unsupported feature warning at timeset.v(32): Initial Construct is not supported and will be ignored
Info: Elaborating entity "stopwatch" for hierarchy "stopwatch:inst2"
Info: Elaborating entity "disp_data_mux" for hierarchy "disp_data_mux:inst8"
Info (10264): Verilog HDL Case Statement information at disp_data_mux.v(60): all case item expressions in this case statement are onehot
Info (10264): Verilog HDL Case Statement information at disp_data_mux.v(74): all case item expressions in this case statement are onehot
Info (10264): Verilog HDL Case Statement information at disp_data_mux.v(88): all case item expressions in this case statement are onehot
Warning (10235): Verilog HDL Always Construct warning at disp_data_mux.v(97): variable "Data" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10240): Verilog HDL Always Construct warning at disp_data_mux.v(40): inferring latch(es) for variable "disp_select", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at disp_data_mux.v(57): inferred latch for "disp_select[5]"
Info (10041): Verilog HDL or VHDL info at disp_data_mux.v(57): inferred latch for "disp_select[4]"
Info (10041): Verilog HDL or VHDL info at disp_data_mux.v(57): inferred latch for "disp_select[3]"
Info (10041): Verilog HDL or VHDL info at disp_data_mux.v(57): inferred latch for "disp_select[2]"
Info (10041): Verilog HDL or VHDL info at disp_data_mux.v(57): inferred latch for "disp_select[1]"
Info (10041): Verilog HDL or VHDL info at disp_data_mux.v(57): inferred latch for "disp_select[0]"
Warning (10240): Verilog HDL Always Construct warning at disp_data_mux.v(40): inferring latch(es) for variable "Data", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at disp_data_mux.v(57): inferred latch for "Data[3]"
Info (10041): Verilog HDL or VHDL info at disp_data_mux.v(57): inferred latch for "Data[2]"
Info (10041): Verilog HDL or VHDL info at disp_data_mux.v(57): inferred latch for "Data[1]"
Info (10041): Verilog HDL or VHDL info at disp_data_mux.v(57): inferred latch for "Data[0]"
Warning: Using design file date_main.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: date_main
Info: Elaborating entity "date_main" for hierarchy "date_main:inst4"
Info: Elaborating entity "datecontrol" for hierarchy "date_main:inst4|datecontrol:inst1"
Info: Elaborating entity "autodate" for hierarchy "date_main:inst4|autodate:inst"
Info: Elaborating entity "setdate" for hierarchy "date_main:inst4|setdate:inst2"
Info: Elaborating entity "time_disp_select" for hierarchy "time_disp_select:inst6"
Warning (10240): Verilog HDL Always Construct warning at time_disp_select.v(45): inferring latch(es) for variable "clk", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at time_disp_select.v(35): inferred latch for "clk"
Warning (10240): Verilog HDL Always Construct warning at time_disp_select.v(45): inferring latch(es) for variable "disp_drive", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at time_disp_select.v(35): inferred latch for "disp_drive[2]"
Info (10041): Verilog HDL or VHDL info at time_disp_select.v(35): inferred latch for "disp_drive[1]"
Info (10041): Verilog HDL or VHDL info at time_disp_select.v(35): inferred latch for "disp_drive[0]"
Info: Duplicate registers merged to single register
    Info: Duplicate register "date_main:inst4|datecontrol:inst1|disp_select[0]" merged to single register "date_main:inst4|datecontrol:inst1|disp_select[1]"
Warning: Reduced register "date_main:inst4|datecontrol:inst1|disp_select[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "date_main:inst4|autodate:inst|month1[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "date_main:inst4|autodate:inst|month1[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "date_main:inst4|autodate:inst|month1[3]" with stuck data_in port to stuck value GND
Info: Power-up level of register "date_main:inst4|datecontrol:inst1|auto_disp_drive[1]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "date_main:inst4|datecontrol:inst1|auto_disp_drive[1]" with stuck data_in port to stuck value VCC
Warning: Latch disp_data_mux:inst8|Data[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal disp_data_mux:inst8|always0~1
Warning: Latch disp_data_mux:inst8|Data[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal disp_data_mux:inst8|always0~1
Warning: Latch disp_data_mux:inst8|Data[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal disp_data_mux:inst8|always0~1
Warning: Latch disp_data_mux:inst8|Data[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal disp_data_mux:inst8|always0~1
Warning: Latch disp_data_mux:inst8|disp_select[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal disp_data_mux:inst8|always0~1
Warning: Latch disp_data_mux:inst8|disp_select[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal disp_data_mux:inst8|always0~1
Warning: Latch disp_data_mux:inst8|disp_select[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal disp_data_mux:inst8|always0~1
Warning: Latch disp_data_mux:inst8|disp_select[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal disp_data_mux:inst8|always0~1
Warning: Latch disp_data_mux:inst8|disp_select[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal disp_data_mux:inst8|always0~1
Warning: Latch disp_data_mux:inst8|disp_select[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal disp_data_mux:inst8|always0~1
Warning: Latch time_disp_select:inst6|disp_drive[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal maincontrol:inst3|Timepiece_EN
Warning: Latch time_disp_select:inst6|disp_drive[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal maincontrol:inst3|Timepiece_EN
Warning: Latch time_disp_select:inst6|disp_drive[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal maincontrol:inst3|Timepiece_EN
Warning: Latch time_disp_select:inst6|clk has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal maincontrol:inst3|Timepiece_EN
Warning: Reduced register "alarmclock:inst11|hour_set1[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "time_auto_and_set:inst1|timeset:inst2|hour_set1[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "date_main:inst4|setdate:inst2|month_set1[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "date_main:inst4|setdate:inst2|day_set1[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "date_main:inst4|datecontrol:inst1|month1[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "time_auto_and_set:inst1|timepiece_main:inst1|hour_counter:inst|hour_data1[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "alarmclock:inst11|hour_set1[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "time_auto_and_set:inst1|timeset:inst2|hour_set1[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "date_main:inst4|setdate:inst2|month_set1[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "date_main:inst4|setdate:inst2|day_set1[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "date_main:inst4|datecontrol:inst1|month1[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "alarmclock:inst11|minute_set1[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "time_auto_and_set:inst1|timepiece_main:inst1|minute_counter:inst1|minute_data1[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "time_auto_and_set:inst1|timeset:inst2|minute_set1[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "alarmclock:inst11|second_set1[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "time_auto_and_set:inst1|timepiece_main:inst1|second_counter:inst2|second_data1[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "time_auto_and_set:inst1|timeset:inst2|second_set1[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "time_auto_and_set:inst1|timepiece_main:inst1|hour_counter:inst|hour_data1[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "date_main:inst4|autodate:inst|day1[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "date_main:inst4|datecontrol:inst1|day1[3]" with stuck data_in port to stuck value GND
Info: Implemented 492 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 14 output pins
    Info: Implemented 474 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 60 warnings
    Info: Processing ended: Sat Jan 19 18:49:31 2008
    Info: Elapsed time: 00:00:21


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; Analysis & Synthesis Suppressed Messages ;
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The suppressed messages can be found in C:/Documents and Settings/zhang/桌面/多功能数字钟/main/main.map.smsg.