top.tan.summary

来自「一些很好的FPGA设计实例」· SUMMARY 代码 · 共 77 行

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : -1.000 ns
From           : load
To             : ffd:inst5|TEMP_DATA_OUT[12]
From Clock     : --
To Clock       : clock
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 18.000 ns
From           : pre_lag:inst2|pre
To             : pre_lag
From Clock     : aIN
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 6.000 ns
From           : load
To             : ffd:inst5|TEMP_DATA_OUT[12]
From Clock     : --
To Clock       : clock
Failed Paths   : 0

Type           : Clock Setup: 'clock'
Slack          : N/A
Required Time  : None
Actual Time    : 100.00 MHz ( period = 10.000 ns )
From           : ffd:inst5|TEMP_DATA_OUT[0]
To             : ffd:inst5|TEMP_DATA_OUT[0]
From Clock     : clock
To Clock       : clock
Failed Paths   : 0

Type           : Clock Setup: 'bIN'
Slack          : N/A
Required Time  : None
Actual Time    : 100.00 MHz ( period = 10.000 ns )
From           : ddiv:inst6|temp
To             : ddiv:inst6|temp
From Clock     : bIN
To Clock       : bIN
Failed Paths   : 0

Type           : Clock Setup: 'aIN'
Slack          : N/A
Required Time  : None
Actual Time    : 100.00 MHz ( period = 10.000 ns )
From           : ddiv:inst8|temp
To             : ddiv:inst8|temp
From Clock     : aIN
To Clock       : aIN
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------