div2.vhd

一些很好的FPGA设计实例

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div2 is
port ( clki : in std_logic;
       clko : inout std_logic
     );
end div2;
architecture behave of div2 is
begin 
process (clki)
variable temp : std_logic_vector(2 downto 0);
   begin
     if (clki'event and clki= '1') then
         if temp = "100" then
            temp := "000";
            clko <= not clko;
         else temp := temp+1;
         end if;
     end if;
end process;
end behave;