top.qsf

一些很好的FPGA设计实例

# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		TOP_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY MAX7000S
set_global_assignment -name DEVICE "EPM7160SLC84-10"
set_global_assignment -name TOP_LEVEL_ENTITY TOP
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:44:58  SEPTEMBER 19, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 6.0
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_location_assignment PIN_83 -to clock
set_location_assignment PIN_40 -to pre_lag
set_location_assignment PIN_49 -to data[0]
set_location_assignment PIN_51 -to data[1]
set_location_assignment PIN_54 -to data[2]
set_location_assignment PIN_56 -to data[3]
set_location_assignment PIN_58 -to data[4]
set_location_assignment PIN_61 -to data[5]
set_location_assignment PIN_64 -to data[6]
set_location_assignment PIN_67 -to data[7]
set_location_assignment PIN_69 -to data[8]
set_location_assignment PIN_73 -to data[9]
set_location_assignment PIN_75 -to data[10]
set_location_assignment PIN_77 -to data[11]
set_location_assignment PIN_81 -to data[12]
set_location_assignment PIN_48 -to f[0]
set_location_assignment PIN_50 -to f[1]
set_location_assignment PIN_52 -to f[2]
set_location_assignment PIN_55 -to f[3]
set_location_assignment PIN_57 -to f[4]
set_location_assignment PIN_60 -to f[5]
set_location_assignment PIN_63 -to f[6]
set_location_assignment PIN_65 -to f[7]
set_location_assignment PIN_68 -to f[8]
set_location_assignment PIN_70 -to f[9]
set_location_assignment PIN_74 -to f[10]
set_location_assignment PIN_76 -to f[11]
set_location_assignment PIN_80 -to f[12]
set_location_assignment PIN_41 -to clc
set_location_assignment PIN_44 -to yihuo
set_location_assignment PIN_4 -to aIN
set_location_assignment PIN_8 -to bIN
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 84
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 10
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD TTL
set_location_assignment PIN_36 -to ain1
set_location_assignment PIN_34 -to bin1
set_location_assignment PIN_10 -to load
set_global_assignment -name VHDL_FILE DDIV.vhd
set_global_assignment -name VHDL_FILE div2.vhd
set_global_assignment -name VHDL_FILE fcount.vhd
set_global_assignment -name VHDL_FILE dcount.vhd
set_global_assignment -name VHDL_FILE ffd.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE TOP0.vwf
set_global_assignment -name VHDL_FILE pre_lag.vhd
set_global_assignment -name BDF_FILE TOP.bdf