dcount.vhd

来自「一些很好的FPGA设计实例」· VHDL 代码 · 共 32 行

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all;
entity dcount is
port(
      clk :  in std_logic;
      sig1 :  in std_logic; --０．５Ｈｚ的闸门信号，可由晶振分频得到
      dcounter : out std_logic_vector (12 downto 0)
     );        --计数输出
end dcount;

architecture data of dcount is
signal  temp : std_logic_vector(12 downto 0) ;
begin 
p1 : process(sig1,clk)
     begin
       if clk'event and clk = '1' then 
          if sig1 = '1' then
          temp <= temp + 1; --在闸门的高电平时段计数
          else 
          temp <= (others=>'0') ;--在闸门的低电平时段清零
          end if;
        end if;
end process p1;

p2 : process(clk,sig1)
       begin
       if sig1'event and sig1 = '0' then
          dcounter <= temp; --在闸门的下降沿将数据读出
       end if;
end process p2;
end data;