top.map.qmsg

一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Oct 15 08:24:57 2007 " "Info: Processing started: Mon Oct 15 08:24:57 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off TOP -c TOP " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off TOP -c TOP" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DDIV.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file DDIV.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ddiv-behave " "Info: Found design unit 1: ddiv-behave" {  } { { "DDIV.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/DDIV.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ddiv " "Info: Found entity 1: ddiv" {  } { { "DDIV.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/DDIV.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file div2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 div2-behave " "Info: Found design unit 1: div2-behave" {  } { { "div2.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/div2.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 div2 " "Info: Found entity 1: div2" {  } { { "div2.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/div2.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fcount.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fcount.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fcount-data " "Info: Found design unit 1: fcount-data" {  } { { "fcount.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/fcount.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fcount " "Info: Found entity 1: fcount" {  } { { "fcount.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/fcount.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dcount.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file dcount.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dcount-data " "Info: Found design unit 1: dcount-data" {  } { { "dcount.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/dcount.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 dcount " "Info: Found entity 1: dcount" {  } { { "dcount.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/dcount.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ffd.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ffd.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ffd-ffd_arch " "Info: Found design unit 1: ffd-ffd_arch" {  } { { "ffd.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/ffd.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ffd " "Info: Found entity 1: ffd" {  } { { "ffd.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/ffd.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pre_lag.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file pre_lag.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pre_lag-data " "Info: Found design unit 1: pre_lag-data" {  } { { "pre_lag.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/pre_lag.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 pre_lag " "Info: Found entity 1: pre_lag" {  } { { "pre_lag.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/pre_lag.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TOP.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file TOP.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 TOP " "Info: Found entity 1: TOP" {  } { { "TOP.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/TOP.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "TOP " "Info: Elaborating entity \"TOP\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pre_lag pre_lag:inst2 " "Info: Elaborating entity \"pre_lag\" for hierarchy \"pre_lag:inst2\"" {  } { { "TOP.bdf" "inst2" { Schematic "C:/Documents and Settings/Administrator/桌面/test/TOP.bdf" { { 240 56 152 336 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddiv ddiv:inst8 " "Info: Elaborating entity \"ddiv\" for hierarchy \"ddiv:inst8\"" {  } { { "TOP.bdf" "inst8" { Schematic "C:/Documents and Settings/Administrator/桌面/test/TOP.bdf" { { -32 -120 -24 64 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div2 div2:inst10 " "Info: Elaborating entity \"div2\" for hierarchy \"div2:inst10\"" {  } { { "TOP.bdf" "inst10" { Schematic "C:/Documents and Settings/Administrator/桌面/test/TOP.bdf" { { -144 72 168 -48 "inst10" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ffd ffd:inst1 " "Info: Elaborating entity \"ffd\" for hierarchy \"ffd:inst1\"" {  } { { "TOP.bdf" "inst1" { Schematic "C:/Documents and Settings/Administrator/桌面/test/TOP.bdf" { { 128 592 808 224 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dcount dcount:inst7 " "Info: Elaborating entity \"dcount\" for hierarchy \"dcount:inst7\"" {  } { { "TOP.bdf" "inst7" { Schematic "C:/Documents and Settings/Administrator/桌面/test/TOP.bdf" { { 160 288 440 256 "inst7" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fcount fcount:inst " "Info: Elaborating entity \"fcount\" for hierarchy \"fcount:inst\"" {  } { { "TOP.bdf" "inst" { Schematic "C:/Documents and Settings/Administrator/桌面/test/TOP.bdf" { { -24 296 440 72 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "dcount:inst7\|temp\[0\]~13 13 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=13) from the following logic: \"dcount:inst7\|temp\[0\]~13\"" {  } { { "dcount.vhd" "temp\[0\]~13" { Text "C:/Documents and Settings/Administrator/桌面/test/dcount.vhd" 17 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "fcount:inst\|temp\[0\]~13 13 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=13) from the following logic: \"fcount:inst\|temp\[0\]~13\"" {  } { { "fcount.vhd" "temp\[0\]~13" { Text "C:/Documents and Settings/Administrator/桌面/test/fcount.vhd" 17 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/altera/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/altera/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/altera/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "dcount:inst7\|lpm_counter:temp_rtl_0 " "Info: Elaborated megafunction instantiation \"dcount:inst7\|lpm_counter:temp_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clock " "Info: Promoted clock signal driven by pin \"clock\" to global clock signal" {  } {  } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0}  } {  } 0 0 "Promoted pin-driven signal(s) to global signal" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "124 " "Info: Implemented 124 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "31 " "Info: Implemented 31 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_MCELLS" "87 " "Info: Implemented 87 macrocells" {  } {  } 0 0 "Implemented %1!d! macrocells" 0 0} { "Info" "ISCL_SCL_TM_SEXPS" "2 " "Info: Implemented 2 shareable expanders" {  } {  } 0 0 "Implemented %1!d! shareable expanders" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 15 08:25:02 2007 " "Info: Processing ended: Mon Oct 15 08:25:02 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}