📄 top.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "aIN register ddiv:inst8\|temp register ddiv:inst8\|temp 100.0 MHz 10.0 ns Internal " "Info: Clock \"aIN\" has Internal fmax of 100.0 MHz between source register \"ddiv:inst8\|temp\" and destination register \"ddiv:inst8\|temp\" (period= 10.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Longest register register " "Info: + Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ddiv:inst8\|temp 1 REG LC80 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC80; Fanout = 15; REG Node = 'ddiv:inst8\|temp'" { } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "" { ddiv:inst8|temp } "NODE_NAME" } } { "DDIV.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/DDIV.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.000 ns) 6.000 ns ddiv:inst8\|temp 2 REG LC80 15 " "Info: 2: + IC(0.000 ns) + CELL(6.000 ns) = 6.000 ns; Loc. = LC80; Fanout = 15; REG Node = 'ddiv:inst8\|temp'" { } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.000 ns" { ddiv:inst8|temp ddiv:inst8|temp } "NODE_NAME" } } { "DDIV.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/DDIV.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns ( 100.00 % ) " "Info: Total cell delay = 6.000 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.000 ns" { ddiv:inst8|temp ddiv:inst8|temp } "NODE_NAME" } } { "f:/altera/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/altera/win/Technology_Viewer.qrui" "6.000 ns" { ddiv:inst8|temp ddiv:inst8|temp } { 0.000ns 0.000ns } { 0.000ns 6.000ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "aIN destination 6.500 ns + Shortest register " "Info: + Shortest clock path from clock \"aIN\" to destination register is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns aIN 1 CLK PIN_4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_4; Fanout = 1; CLK Node = 'aIN'" { } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "" { aIN } "NODE_NAME" } } { "TOP.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/TOP.bdf" { { -8 -488 -320 8 "aIN" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns ddiv:inst8\|temp 2 REG LC80 15 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC80; Fanout = 15; REG Node = 'ddiv:inst8\|temp'" { } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.000 ns" { aIN ddiv:inst8|temp } "NODE_NAME" } } { "DDIV.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/DDIV.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns ( 84.62 % ) " "Info: Total cell delay = 5.500 ns ( 84.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 15.38 % ) " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.500 ns" { aIN ddiv:inst8|temp } "NODE_NAME" } } { "f:/altera/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/altera/win/Technology_Viewer.qrui" "6.500 ns" { aIN aIN~out ddiv:inst8|temp } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "aIN source 6.500 ns - Longest register " "Info: - Longest clock path from clock \"aIN\" to source register is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns aIN 1 CLK PIN_4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_4; Fanout = 1; CLK Node = 'aIN'" { } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "" { aIN } "NODE_NAME" } } { "TOP.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/TOP.bdf" { { -8 -488 -320 8 "aIN" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns ddiv:inst8\|temp 2 REG LC80 15 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC80; Fanout = 15; REG Node = 'ddiv:inst8\|temp'" { } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.000 ns" { aIN ddiv:inst8|temp } "NODE_NAME" } } { "DDIV.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/DDIV.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns ( 84.62 % ) " "Info: Total cell delay = 5.500 ns ( 84.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 15.38 % ) " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.500 ns" { aIN ddiv:inst8|temp } "NODE_NAME" } } { "f:/altera/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/altera/win/Technology_Viewer.qrui" "6.500 ns" { aIN aIN~out ddiv:inst8|temp } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.500 ns" { aIN ddiv:inst8|temp } "NODE_NAME" } } { "f:/altera/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/altera/win/Technology_Viewer.qrui" "6.500 ns" { aIN aIN~out ddiv:inst8|temp } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.500 ns" { aIN ddiv:inst8|temp } "NODE_NAME" } } { "f:/altera/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/altera/win/Technology_Viewer.qrui" "6.500 ns" { aIN aIN~out ddiv:inst8|temp } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" { } { { "DDIV.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/DDIV.vhd" 14 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" { } { { "DDIV.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/DDIV.vhd" 14 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.000 ns" { ddiv:inst8|temp ddiv:inst8|temp } "NODE_NAME" } } { "f:/altera/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/altera/win/Technology_Viewer.qrui" "6.000 ns" { ddiv:inst8|temp ddiv:inst8|temp } { 0.000ns 0.000ns } { 0.000ns 6.000ns } } } { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.500 ns" { aIN ddiv:inst8|temp } "NODE_NAME" } } { "f:/altera/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/altera/win/Technology_Viewer.qrui" "6.500 ns" { aIN aIN~out ddiv:inst8|temp } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.500 ns" { aIN ddiv:inst8|temp } "NODE_NAME" } } { "f:/altera/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/altera/win/Technology_Viewer.qrui" "6.500 ns" { aIN aIN~out ddiv:inst8|temp } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "bIN register ddiv:inst6\|temp register ddiv:inst6\|temp 100.0 MHz 10.0 ns Internal " "Info: Clock \"bIN\" has Internal fmax of 100.0 MHz between source register \"ddiv:inst6\|temp\" and destination register \"ddiv:inst6\|temp\" (period= 10.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Longest register register " "Info: + Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ddiv:inst6\|temp 1 REG LC75 53 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC75; Fanout = 53; REG Node = 'ddiv:inst6\|temp'" { } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "" { ddiv:inst6|temp } "NODE_NAME" } } { "DDIV.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/DDIV.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.000 ns) 6.000 ns ddiv:inst6\|temp 2 REG LC75 53 " "Info: 2: + IC(0.000 ns) + CELL(6.000 ns) = 6.000 ns; Loc. = LC75; Fanout = 53; REG Node = 'ddiv:inst6\|temp'" { } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.000 ns" { ddiv:inst6|temp ddiv:inst6|temp } "NODE_NAME" } } { "DDIV.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/DDIV.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns ( 100.00 % ) " "Info: Total cell delay = 6.000 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.000 ns" { ddiv:inst6|temp ddiv:inst6|temp } "NODE_NAME" } } { "f:/altera/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/altera/win/Technology_Viewer.qrui" "6.000 ns" { ddiv:inst6|temp ddiv:inst6|temp } { 0.000ns 0.000ns } { 0.000ns 6.000ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "bIN destination 6.500 ns + Shortest register " "Info: + Shortest clock path from clock \"bIN\" to destination register is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns bIN 1 CLK PIN_8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_8; Fanout = 1; CLK Node = 'bIN'" { } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "" { bIN } "NODE_NAME" } } { "TOP.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/TOP.bdf" { { 152 -480 -312 168 "bIN" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns ddiv:inst6\|temp 2 REG LC75 53 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC75; Fanout = 53; REG Node = 'ddiv:inst6\|temp'" { } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.000 ns" { bIN ddiv:inst6|temp } "NODE_NAME" } } { "DDIV.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/DDIV.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns ( 84.62 % ) " "Info: Total cell delay = 5.500 ns ( 84.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 15.38 % ) " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.500 ns" { bIN ddiv:inst6|temp } "NODE_NAME" } } { "f:/altera/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/altera/win/Technology_Viewer.qrui" "6.500 ns" { bIN bIN~out ddiv:inst6|temp } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "bIN source 6.500 ns - Longest register " "Info: - Longest clock path from clock \"bIN\" to source register is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns bIN 1 CLK PIN_8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_8; Fanout = 1; CLK Node = 'bIN'" { } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "" { bIN } "NODE_NAME" } } { "TOP.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/TOP.bdf" { { 152 -480 -312 168 "bIN" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns ddiv:inst6\|temp 2 REG LC75 53 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC75; Fanout = 53; REG Node = 'ddiv:inst6\|temp'" { } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.000 ns" { bIN ddiv:inst6|temp } "NODE_NAME" } } { "DDIV.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/DDIV.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns ( 84.62 % ) " "Info: Total cell delay = 5.500 ns ( 84.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 15.38 % ) " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.500 ns" { bIN ddiv:inst6|temp } "NODE_NAME" } } { "f:/altera/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/altera/win/Technology_Viewer.qrui" "6.500 ns" { bIN bIN~out ddiv:inst6|temp } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.500 ns" { bIN ddiv:inst6|temp } "NODE_NAME" } } { "f:/altera/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/altera/win/Technology_Viewer.qrui" "6.500 ns" { bIN bIN~out ddiv:inst6|temp } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.500 ns" { bIN ddiv:inst6|temp } "NODE_NAME" } } { "f:/altera/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/altera/win/Technology_Viewer.qrui" "6.500 ns" { bIN bIN~out ddiv:inst6|temp } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" { } { { "DDIV.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/DDIV.vhd" 14 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" { } { { "DDIV.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/DDIV.vhd" 14 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.000 ns" { ddiv:inst6|temp ddiv:inst6|temp } "NODE_NAME" } } { "f:/altera/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/altera/win/Technology_Viewer.qrui" "6.000 ns" { ddiv:inst6|temp ddiv:inst6|temp } { 0.000ns 0.000ns } { 0.000ns 6.000ns } } } { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.500 ns" { bIN ddiv:inst6|temp } "NODE_NAME" } } { "f:/altera/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/altera/win/Technology_Viewer.qrui" "6.500 ns" { bIN bIN~out ddiv:inst6|temp } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.500 ns" { bIN ddiv:inst6|temp } "NODE_NAME" } } { "f:/altera/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/altera/win/Technology_Viewer.qrui" "6.500 ns" { bIN bIN~out ddiv:inst6|temp } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register ffd:inst5\|TEMP_DATA_OUT\[0\] register ffd:inst5\|TEMP_DATA_OUT\[0\] 100.0 MHz 10.0 ns Internal " "Info: Clock \"clock\" has Internal fmax of 100.0 MHz between source register \"ffd:inst5\|TEMP_DATA_OUT\[0\]\" and destination register \"ffd:inst5\|TEMP_DATA_OUT\[0\]\" (period= 10.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Longest register register " "Info: + Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ffd:inst5\|TEMP_DATA_OUT\[0\] 1 REG LC88 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC88; Fanout = 2; REG Node = 'ffd:inst5\|TEMP_DATA_OUT\[0\]'" { } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "" { ffd:inst5|TEMP_DATA_OUT[0] } "NODE_NAME" } } { "ffd.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/ffd.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns ffd:inst5\|TEMP_DATA_OUT\[0\] 2 REG LC88 2 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC88; Fanout = 2; REG Node = 'ffd:inst5\|TEMP_DATA_OUT\[0\]'" { } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.000 ns" { ffd:inst5|TEMP_DATA_OUT[0] ffd:inst5|TEMP_DATA_OUT[0] } "NODE_NAME" } } { "ffd.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/ffd.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 83.33 % ) " "Info: Total cell delay = 5.000 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 1.000 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.000 ns" { ffd:inst5|TEMP_DATA_OUT[0] ffd:inst5|TEMP_DATA_OUT[0] } "NODE_NAME" } } { "f:/altera/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/altera/win/Technology_Viewer.qrui" "6.000 ns" { ffd:inst5|TEMP_DATA_OUT[0] ffd:inst5|TEMP_DATA_OUT[0] } { 0.000ns 1.000ns } { 0.000ns 5.000ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 9.500 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 9.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clock 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clock'" { } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "TOP.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/TOP.bdf" { { -120 -104 64 -104 "clock" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.500 ns div2:inst10\|clko~reg0 2 REG LC67 54 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.500 ns; Loc. = LC67; Fanout = 54; REG Node = 'div2:inst10\|clko~reg0'" { } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "2.000 ns" { clock div2:inst10|clko~reg0 } "NODE_NAME" } } { "div2.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/div2.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 9.500 ns ffd:inst5\|TEMP_DATA_OUT\[0\] 3 REG LC88 2 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 9.500 ns; Loc. = LC88; Fanout = 2; REG Node = 'ffd:inst5\|TEMP_DATA_OUT\[0\]'" { } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.000 ns" { div2:inst10|clko~reg0 ffd:inst5|TEMP_DATA_OUT[0] } "NODE_NAME" } } { "ffd.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/ffd.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.500 ns ( 89.47 % ) " "Info: Total cell delay = 8.500 ns ( 89.47 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 10.53 % ) " "Info: Total interconnect delay = 1.000 ns ( 10.53 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "9.500 ns" { clock div2:inst10|clko~reg0 ffd:inst5|TEMP_DATA_OUT[0] } "NODE_NAME" } } { "f:/altera/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/altera/win/Technology_Viewer.qrui" "9.500 ns" { clock clock~out div2:inst10|clko~reg0 ffd:inst5|TEMP_DATA_OUT[0] } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 9.500 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 9.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clock 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clock'" { } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "TOP.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/TOP.bdf" { { -120 -104 64 -104 "clock" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.500 ns div2:inst10\|clko~reg0 2 REG LC67 54 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.500 ns; Loc. = LC67; Fanout = 54; REG Node = 'div2:inst10\|clko~reg0'" { } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "2.000 ns" { clock div2:inst10|clko~reg0 } "NODE_NAME" } } { "div2.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/div2.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 9.500 ns ffd:inst5\|TEMP_DATA_OUT\[0\] 3 REG LC88 2 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 9.500 ns; Loc. = LC88; Fanout = 2; REG Node = 'ffd:inst5\|TEMP_DATA_OUT\[0\]'" { } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.000 ns" { div2:inst10|clko~reg0 ffd:inst5|TEMP_DATA_OUT[0] } "NODE_NAME" } } { "ffd.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/ffd.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.500 ns ( 89.47 % ) " "Info: Total cell delay = 8.500 ns ( 89.47 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 10.53 % ) " "Info: Total interconnect delay = 1.000 ns ( 10.53 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "9.500 ns" { clock div2:inst10|clko~reg0 ffd:inst5|TEMP_DATA_OUT[0] } "NODE_NAME" } } { "f:/altera/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/altera/win/Technology_Viewer.qrui" "9.500 ns" { clock clock~out div2:inst10|clko~reg0 ffd:inst5|TEMP_DATA_OUT[0] } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "9.500 ns" { clock div2:inst10|clko~reg0 ffd:inst5|TEMP_DATA_OUT[0] } "NODE_NAME" } } { "f:/altera/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/altera/win/Technology_Viewer.qrui" "9.500 ns" { clock clock~out div2:inst10|clko~reg0 ffd:inst5|TEMP_DATA_OUT[0] } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } } } { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "9.500 ns" { clock div2:inst10|clko~reg0 ffd:inst5|TEMP_DATA_OUT[0] } "NODE_NAME" } } { "f:/altera/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/altera/win/Technology_Viewer.qrui" "9.500 ns" { clock clock~out div2:inst10|clko~reg0 ffd:inst5|TEMP_DATA_OUT[0] } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" { } { { "ffd.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/ffd.vhd" 22 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" { } { { "ffd.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/ffd.vhd" 22 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.000 ns" { ffd:inst5|TEMP_DATA_OUT[0] ffd:inst5|TEMP_DATA_OUT[0] } "NODE_NAME" } } { "f:/altera/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/altera/win/Technology_Viewer.qrui" "6.000 ns" { ffd:inst5|TEMP_DATA_OUT[0] ffd:inst5|TEMP_DATA_OUT[0] } { 0.000ns 1.000ns } { 0.000ns 5.000ns } } } { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "9.500 ns" { clock div2:inst10|clko~reg0 ffd:inst5|TEMP_DATA_OUT[0] } "NODE_NAME" } } { "f:/altera/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/altera/win/Technology_Viewer.qrui" "9.500 ns" { clock clock~out div2:inst10|clko~reg0 ffd:inst5|TEMP_DATA_OUT[0] } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } } } { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "9.500 ns" { clock div2:inst10|clko~reg0 ffd:inst5|TEMP_DATA_OUT[0] } "NODE_NAME" } } { "f:/altera/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/altera/win/Technology_Viewer.qrui" "9.500 ns" { clock clock~out div2:inst10|clko~reg0 ffd:inst5|TEMP_DATA_OUT[0] } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "ffd:inst1\|TEMP_DATA_OUT\[0\] load clock -1.000 ns register " "Info: tsu for register \"ffd:inst1\|TEMP_DATA_OUT\[0\]\" (data pin = \"load\", clock pin = \"clock\") is -1.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns + Longest pin register " "Info: + Longest pin to register delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns load 1 PIN PIN_10 52 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_10; Fanout = 52; PIN Node = 'load'" { } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "" { load } "NODE_NAME" } } { "TOP.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/TOP.bdf" { { 48 704 872 64 "load" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns ffd:inst1\|TEMP_DATA_OUT\[0\] 2 REG LC91 2 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC91; Fanout = 2; REG Node = 'ffd:inst1\|TEMP_DATA_OUT\[0\]'" { } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.000 ns" { load ffd:inst1|TEMP_DATA_OUT[0] } "NODE_NAME" } } { "ffd.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/ffd.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns ( 84.62 % ) " "Info: Total cell delay = 5.500 ns ( 84.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 15.38 % ) " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.500 ns" { load ffd:inst1|TEMP_DATA_OUT[0] } "NODE_NAME" } } { "f:/altera/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/altera/win/Technology_Viewer.qrui" "6.500 ns" { load load~out ffd:inst1|TEMP_DATA_OUT[0] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" { } { { "ffd.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/ffd.vhd" 22 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 9.500 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 9.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clock 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clock'" { } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "TOP.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/TOP.bdf" { { -120 -104 64 -104 "clock" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.500 ns div2:inst10\|clko~reg0 2 REG LC67 54 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.500 ns; Loc. = LC67; Fanout = 54; REG Node = 'div2:inst10\|clko~reg0'" { } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "2.000 ns" { clock div2:inst10|clko~reg0 } "NODE_NAME" } } { "div2.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/div2.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 9.500 ns ffd:inst1\|TEMP_DATA_OUT\[0\] 3 REG LC91 2 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 9.500 ns; Loc. = LC91; Fanout = 2; REG Node = 'ffd:inst1\|TEMP_DATA_OUT\[0\]'" { } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.000 ns" { div2:inst10|clko~reg0 ffd:inst1|TEMP_DATA_OUT[0] } "NODE_NAME" } } { "ffd.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/ffd.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.500 ns ( 89.47 % ) " "Info: Total cell delay = 8.500 ns ( 89.47 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 10.53 % ) " "Info: Total interconnect delay = 1.000 ns ( 10.53 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "9.500 ns" { clock div2:inst10|clko~reg0 ffd:inst1|TEMP_DATA_OUT[0] } "NODE_NAME" } } { "f:/altera/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/altera/win/Technology_Viewer.qrui" "9.500 ns" { clock clock~out div2:inst10|clko~reg0 ffd:inst1|TEMP_DATA_OUT[0] } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "6.500 ns" { load ffd:inst1|TEMP_DATA_OUT[0] } "NODE_NAME" } } { "f:/altera/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/altera/win/Technology_Viewer.qrui" "6.500 ns" { load load~out ffd:inst1|TEMP_DATA_OUT[0] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } { "f:/altera/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/altera/win/TimingClosureFloorplan.fld" "" "9.500 ns" { clock div2:inst10|clko~reg0 ffd:inst1|TEMP_DATA_OUT[0] } "NODE_NAME" } } { "f:/altera/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/altera/win/Technology_Viewer.qrui" "9.500 ns" { clock clock~out div2:inst10|clko~reg0 ffd:inst1|TEMP_DATA_OUT[0] } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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