top.tan.qmsg

一些很好的FPGA设计实例

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "aIN " "Info: Assuming node \"aIN\" is an undefined clock" {  } { { "TOP.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/TOP.bdf" { { -8 -488 -320 8 "aIN" "" } } } } { "f:/altera/altera/win/Assignment Editor.qase" "" { Assignment "f:/altera/altera/win/Assignment Editor.qase" 1 { { 0 "aIN" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "bIN " "Info: Assuming node \"bIN\" is an undefined clock" {  } { { "TOP.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/TOP.bdf" { { 152 -480 -312 168 "bIN" "" } } } } { "f:/altera/altera/win/Assignment Editor.qase" "" { Assignment "f:/altera/altera/win/Assignment Editor.qase" 1 { { 0 "bIN" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "TOP.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/TOP.bdf" { { -120 -104 64 -104 "clock" "" } } } } { "f:/altera/altera/win/Assignment Editor.qase" "" { Assignment "f:/altera/altera/win/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "7 " "Warning: Found 7 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "inst11~63 " "Info: Detected gated clock \"inst11~63\" as buffer" {  } { { "TOP.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/TOP.bdf" { { 128 56 120 176 "inst11" "" } } } } { "f:/altera/altera/win/Assignment Editor.qase" "" { Assignment "f:/altera/altera/win/Assignment Editor.qase" 1 { { 0 "inst11~63" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "inst11~62 " "Info: Detected gated clock \"inst11~62\" as buffer" {  } { { "TOP.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/TOP.bdf" { { 128 56 120 176 "inst11" "" } } } } { "f:/altera/altera/win/Assignment Editor.qase" "" { Assignment "f:/altera/altera/win/Assignment Editor.qase" 1 { { 0 "inst11~62" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "inst11~33 " "Info: Detected gated clock \"inst11~33\" as buffer" {  } { { "TOP.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/TOP.bdf" { { 128 56 120 176 "inst11" "" } } } } { "f:/altera/altera/win/Assignment Editor.qase" "" { Assignment "f:/altera/altera/win/Assignment Editor.qase" 1 { { 0 "inst11~33" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "inst11~32 " "Info: Detected gated clock \"inst11~32\" as buffer" {  } { { "TOP.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/TOP.bdf" { { 128 56 120 176 "inst11" "" } } } } { "f:/altera/altera/win/Assignment Editor.qase" "" { Assignment "f:/altera/altera/win/Assignment Editor.qase" 1 { { 0 "inst11~32" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "div2:inst10\|clko~reg0 " "Info: Detected ripple clock \"div2:inst10\|clko~reg0\" as buffer" {  } { { "div2.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/div2.vhd" 14 -1 0 } } { "f:/altera/altera/win/Assignment Editor.qase" "" { Assignment "f:/altera/altera/win/Assignment Editor.qase" 1 { { 0 "div2:inst10\|clko~reg0" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ddiv:inst6\|temp " "Info: Detected ripple clock \"ddiv:inst6\|temp\" as buffer" {  } { { "DDIV.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/DDIV.vhd" 14 -1 0 } } { "f:/altera/altera/win/Assignment Editor.qase" "" { Assignment "f:/altera/altera/win/Assignment Editor.qase" 1 { { 0 "ddiv:inst6\|temp" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ddiv:inst8\|temp " "Info: Detected ripple clock \"ddiv:inst8\|temp\" as buffer" {  } { { "DDIV.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/DDIV.vhd" 14 -1 0 } } { "f:/altera/altera/win/Assignment Editor.qase" "" { Assignment "f:/altera/altera/win/Assignment Editor.qase" 1 { { 0 "ddiv:inst8\|temp" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}