📄 top.sim.vwf

📁 一些很好的FPGA设计实例
💻 VWF
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		REPEAT = 1;
		LEVEL 0 FOR 1000000000.0;
	}
}

TRANSITION_LIST("f[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000000000.0;
	}
}

TRANSITION_LIST("f[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000000000.0;
	}
}

TRANSITION_LIST("f[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000000000.0;
	}
}

TRANSITION_LIST("f[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000000000.0;
	}
}

TRANSITION_LIST("f[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 22284513.0;
		LEVEL 1 FOR 977715487.0;
	}
}

TRANSITION_LIST("f[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 22284513.0;
		LEVEL 1 FOR 29060000.0;
		LEVEL 0 FOR 948655487.0;
	}
}

TRANSITION_LIST("f[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000000000.0;
	}
}

TRANSITION_LIST("pre_lag")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 18.0;
		LEVEL 1 FOR 999999982.0;
	}
}

TRANSITION_LIST("clock")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 1000000;
			LEVEL 0 FOR 500.0;
			LEVEL 1 FOR 500.0;
		}
	}
}

TRANSITION_LIST("aIN")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 64;
			LEVEL 0 FOR 7700000.0;
			LEVEL 1 FOR 7700000.0;
		}
		LEVEL 0 FOR 7700000.0;
		LEVEL 1 FOR 6700000.0;
	}
}

TRANSITION_LIST("bIN")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 12840000.0;
		LEVEL 1 FOR 7700000.0;
		NODE
		{
			REPEAT = 63;
			LEVEL 0 FOR 7700000.0;
			LEVEL 1 FOR 7700000.0;
		}
		LEVEL 0 FOR 7700000.0;
		LEVEL 1 FOR 1560000.0;
	}
}

TRANSITION_LIST("clc")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 4505.0;
		NODE
		{
			REPEAT = 99999;
			LEVEL 1 FOR 5000.0;
			LEVEL 0 FOR 5000.0;
		}
		LEVEL 1 FOR 5000.0;
		LEVEL 0 FOR 495.0;
	}
}

TRANSITION_LIST("yihuo")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 15400018.0;
		NODE
		{
			REPEAT = 63;
			LEVEL 0 FOR 5140000.0;
			LEVEL 1 FOR 10260000.0;
		}
		LEVEL 0 FOR 5140000.0;
		LEVEL 1 FOR 9259982.0;
	}
}

TRANSITION_LIST("bin1")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 10.0;
		NODE
		{
			REPEAT = 32;
			LEVEL 1 FOR 15400000.0;
			LEVEL 0 FOR 15400000.0;
		}
		LEVEL 1 FOR 14399990.0;
	}
}

TRANSITION_LIST("ain1")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 20540000.0;
		NODE
		{
			REPEAT = 31;
			LEVEL 0 FOR 15400000.0;
			LEVEL 1 FOR 15400000.0;
		}
		LEVEL 0 FOR 15400000.0;
		LEVEL 1 FOR 9259990.0;
	}
}

TRANSITION_LIST("load")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 22282240.0;
		LEVEL 1 FOR 543948800.0;
		LEVEL 0 FOR 27525120.0;
		LEVEL 1 FOR 406243840.0;
	}
}

DISPLAY_LINE
{
	CHANNEL = "data";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
	CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13;
}

DISPLAY_LINE
{
	CHANNEL = "data[12]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 1;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "data[11]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 2;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "data[10]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 3;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "data[9]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 4;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "data[8]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 5;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "data[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 6;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "data[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 7;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "data[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 8;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "data[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 9;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "data[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 10;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "data[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 11;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "data[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 12;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "data[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 13;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "f";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 14;
	TREE_LEVEL = 0;
	CHILDREN = 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27;
}

DISPLAY_LINE
{
	CHANNEL = "f[12]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 15;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "f[11]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 16;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "f[10]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 17;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "f[9]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 18;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "f[8]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 19;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "f[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 20;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "f[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 21;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "f[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 22;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "f[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 23;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "f[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 24;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "f[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 25;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "f[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 26;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "f[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 27;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "pre_lag";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 28;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "clock";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 29;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "aIN";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 30;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "bIN";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 31;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "clc";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 32;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "yihuo";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 33;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "bin1";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 34;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "ain1";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 35;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "load";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 36;
	TREE_LEVEL = 0;
}

TIME_BAR
{
	TIME = 0;
	MASTER = TRUE;
}
;
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💿 文件大小 21188 K
👤 上传用户 cpu686
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#FPGA #设计实例
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