top.map.rpt

一些很好的FPGA设计实例

; Maximum fan-out      ; 53                    ;
; Total fan-out        ; 462                   ;
; Average fan-out      ; 3.73                  ;
+----------------------+-----------------------+


+-----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                           ;
+--------------------------------+------------+------+------------------------------------------+
; Compilation Hierarchy Node     ; Macrocells ; Pins ; Full Hierarchy Name                      ;
+--------------------------------+------------+------+------------------------------------------+
; |TOP                           ; 87         ; 35   ; |TOP                                     ;
;    |dcount:inst7|              ; 26         ; 0    ; |TOP|dcount:inst7                        ;
;       |lpm_counter:temp_rtl_0| ; 13         ; 0    ; |TOP|dcount:inst7|lpm_counter:temp_rtl_0 ;
;    |ddiv:inst6|                ; 1          ; 0    ; |TOP|ddiv:inst6                          ;
;    |ddiv:inst8|                ; 1          ; 0    ; |TOP|ddiv:inst8                          ;
;    |div2:inst10|               ; 4          ; 0    ; |TOP|div2:inst10                         ;
;    |fcount:inst|               ; 26         ; 0    ; |TOP|fcount:inst                         ;
;       |lpm_counter:temp_rtl_1| ; 13         ; 0    ; |TOP|fcount:inst|lpm_counter:temp_rtl_1  ;
;    |ffd:inst1|                 ; 13         ; 0    ; |TOP|ffd:inst1                           ;
;    |ffd:inst5|                 ; 13         ; 0    ; |TOP|ffd:inst5                           ;
;    |pre_lag:inst2|             ; 1          ; 0    ; |TOP|pre_lag:inst2                       ;
+--------------------------------+------------+------+------------------------------------------+


+--------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: dcount:inst7|lpm_counter:temp_rtl_0 ;
+------------------------+-------------------+-----------------------------------------+
; Parameter Name         ; Value             ; Type                                    ;
+------------------------+-------------------+-----------------------------------------+
; AUTO_CARRY_CHAINS      ; ON                ; AUTO_CARRY                              ;
; IGNORE_CARRY_BUFFERS   ; OFF               ; IGNORE_CARRY                            ;
; AUTO_CASCADE_CHAINS    ; ON                ; AUTO_CASCADE                            ;
; IGNORE_CASCADE_BUFFERS ; OFF               ; IGNORE_CASCADE                          ;
; LPM_WIDTH              ; 13                ; Untyped                                 ;
; LPM_DIRECTION          ; UP                ; Untyped                                 ;
; LPM_MODULUS            ; 0                 ; Untyped                                 ;
; LPM_AVALUE             ; UNUSED            ; Untyped                                 ;
; LPM_SVALUE             ; UNUSED            ; Untyped                                 ;
; LPM_PORT_UPDOWN        ; PORT_CONNECTIVITY ; Untyped                                 ;
; DEVICE_FAMILY          ; MAX7000S          ; Untyped                                 ;
; CARRY_CHAIN            ; MANUAL            ; Untyped                                 ;
; CARRY_CHAIN_LENGTH     ; 48                ; CARRY_CHAIN_LENGTH                      ;
; NOT_GATE_PUSH_BACK     ; ON                ; NOT_GATE_PUSH_BACK                      ;
; CARRY_CNT_EN           ; SMART             ; Untyped                                 ;
; LABWIDE_SCLR           ; ON                ; Untyped                                 ;
; USE_NEW_VERSION        ; TRUE              ; Untyped                                 ;
; CBXI_PARAMETER         ; NOTHING           ; Untyped                                 ;
+------------------------+-------------------+-----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: fcount:inst|lpm_counter:temp_rtl_1 ;
+------------------------+-------------------+----------------------------------------+
; Parameter Name         ; Value             ; Type                                   ;
+------------------------+-------------------+----------------------------------------+
; AUTO_CARRY_CHAINS      ; ON                ; AUTO_CARRY                             ;
; IGNORE_CARRY_BUFFERS   ; OFF               ; IGNORE_CARRY                           ;
; AUTO_CASCADE_CHAINS    ; ON                ; AUTO_CASCADE                           ;
; IGNORE_CASCADE_BUFFERS ; OFF               ; IGNORE_CASCADE                         ;
; LPM_WIDTH              ; 13                ; Untyped                                ;
; LPM_DIRECTION          ; UP                ; Untyped                                ;
; LPM_MODULUS            ; 0                 ; Untyped                                ;
; LPM_AVALUE             ; UNUSED            ; Untyped                                ;
; LPM_SVALUE             ; UNUSED            ; Untyped                                ;
; LPM_PORT_UPDOWN        ; PORT_CONNECTIVITY ; Untyped                                ;
; DEVICE_FAMILY          ; MAX7000S          ; Untyped                                ;
; CARRY_CHAIN            ; MANUAL            ; Untyped                                ;
; CARRY_CHAIN_LENGTH     ; 48                ; CARRY_CHAIN_LENGTH                     ;
; NOT_GATE_PUSH_BACK     ; ON                ; NOT_GATE_PUSH_BACK                     ;
; CARRY_CNT_EN           ; SMART             ; Untyped                                ;
; LABWIDE_SCLR           ; ON                ; Untyped                                ;
; USE_NEW_VERSION        ; TRUE              ; Untyped                                ;
; CBXI_PARAMETER         ; NOTHING           ; Untyped                                ;
+------------------------+-------------------+----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon Oct 15 08:24:57 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off TOP -c TOP
Info: Found 2 design units, including 1 entities, in source file DDIV.vhd
    Info: Found design unit 1: ddiv-behave
    Info: Found entity 1: ddiv
Info: Found 2 design units, including 1 entities, in source file div2.vhd
    Info: Found design unit 1: div2-behave
    Info: Found entity 1: div2
Info: Found 2 design units, including 1 entities, in source file fcount.vhd
    Info: Found design unit 1: fcount-data
    Info: Found entity 1: fcount
Info: Found 2 design units, including 1 entities, in source file dcount.vhd
    Info: Found design unit 1: dcount-data
    Info: Found entity 1: dcount
Info: Found 2 design units, including 1 entities, in source file ffd.vhd
    Info: Found design unit 1: ffd-ffd_arch
    Info: Found entity 1: ffd
Info: Found 2 design units, including 1 entities, in source file pre_lag.vhd
    Info: Found design unit 1: pre_lag-data
    Info: Found entity 1: pre_lag
Info: Found 1 design units, including 1 entities, in source file TOP.bdf
    Info: Found entity 1: TOP
Info: Elaborating entity "TOP" for the top level hierarchy
Info: Elaborating entity "pre_lag" for hierarchy "pre_lag:inst2"
Info: Elaborating entity "ddiv" for hierarchy "ddiv:inst8"
Info: Elaborating entity "div2" for hierarchy "div2:inst10"
Info: Elaborating entity "ffd" for hierarchy "ffd:inst1"
Info: Elaborating entity "dcount" for hierarchy "dcount:inst7"
Info: Elaborating entity "fcount" for hierarchy "fcount:inst"
Info: Inferred 2 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=13) from the following logic: "dcount:inst7|temp[0]~13"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=13) from the following logic: "fcount:inst|temp[0]~13"
Info: Found 1 design units, including 1 entities, in source file f:/altera/altera/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Elaborated megafunction instantiation "dcount:inst7|lpm_counter:temp_rtl_0"
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clock" to global clock signal
Info: Implemented 124 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 31 output pins
    Info: Implemented 87 macrocells
    Info: Implemented 2 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Mon Oct 15 08:25:02 2007
    Info: Elapsed time: 00:00:06