sel.vhd

来自「一些很好的FPGA设计实例」· VHDL 代码 · 共 42 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity  sel is
port (
     clr : in std_logic; 
      V1 : in std_logic;
      I1 : in std_logic;  
      V2 : in std_logic;
      I2 : in std_logic;
      V3 : in std_logic;
      I3 : in std_logic;
     sele: in std_logic_vector(1 downto 0);
      a  : out std_logic;
      b  : out std_logic
     );
end sel;
architecture data of sel is
begin 
   process(sele,clr) 
  begin
   if(clr = '1')then
           a  <= '0';  
           b  <= '0';
   else
     case sele is
         when "00" =>
           a  <= V1;  
           b  <= I1;
         when "01" =>
           a  <= V2;  
           b  <= I2;
         when "10" =>
           a  <= V3;  
           b  <= I3;
         when others =>
           a  <= '0';  
           b  <= '0';
         end case; 
      end if;
   end process;
end data;