da.vhd

来自「一些很好的FPGA设计实例」· VHDL 代码 · 共 31 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity  data is
port (
      sele:in std_logic;
      hold: in std_logic;
      dcounter: in std_logic_vector(12 downto 0);
      fcounter: in std_logic_vector(12 downto 0);
      data  :  out std_logic_vector(12 downto 0)
     );
end data;
architecture data of data is
signal temp : std_logic_vector(12 downto 0);
begin 
process(hold,sele)
 begin
  if hold <= '0' then
     temp <=  "0000000000000" ;
  else
     if sele = '1' then
         temp  <= dcounter ;
     elsif sele = '1' then
         temp  <= fcounter ;
     else
         temp  <= "0000000000000";
     end if;
   end if;
   data <= temp;
 end process;
end data;