pre_lag.vhd

一些很好的FPGA设计实例

library ieee; 
use ieee.std_logic_1164.all; 
entity pre_lag is 
port( 
    s1,s2 : in std_logic;--两输入信号 
      pre : out std_logic
    );                --判断结果输出 
end pre_lag; 
architecture data of pre_lag is 
begin 
lag:process(s1) 
begin 
    if  s1'event and s1 = '1' then
         if s2 = '0' then
         pre <= '1';--若s1超前s2,输出为 ′1′，否则输出′0