ffd.vhd

来自「一些很好的FPGA设计实例」· VHDL 代码 · 共 34 行

library IEEE;
use IEEE.std_logic_1164.all;

entity ffd is
port (
LOAD : in std_logic;
CLK : in std_logic;
DATA_IN : in std_logic_vector (12 downto 0);
DATA_OUT : out std_logic_vector (12 downto 0)
);
end entity;



architecture ffd_arch of ffd is
signal TEMP_DATA_OUT: std_logic_vector (12 downto 0);
begin

process (CLK)
begin

if rising_edge(CLK) then
if LOAD = '1' then
TEMP_DATA_OUT <= DATA_IN;
end if;
end if;

end process;

DATA_OUT <= TEMP_DATA_OUT;

end architecture;