f.vhd

来自「一些很好的FPGA设计实例」· VHDL 代码 · 共 37 行

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all;
entity fcount is
port(
      clk :  in   std_logic;
      sig :  in   std_logic; 
      rst :  in   std_logic;
     hold :  out  std_logic;
      fcounter : out std_logic_vector (12 downto 0)
     );        --计数输出
end fcount;

architecture data of fcount is
signal  temp : std_logic_vector(12 downto 0) ;
begin 
p1 : process(sig,clk,rst)
     begin
      if ( rst = '1') then
          temp <=(others=>'0') ;
      elsif clk'event and clk = '1' then 
          if sig = '1' then
          temp <= temp + 1; --在闸门的高电平时段计数
          else 
          temp <= (others=>'0') ;--在闸门的低电平时段清零
          end if;
      end if;
end process p1;

p2 : process(sig)
       begin
       if sig'event and sig = '0' then
          hold <= '1';
          fcounter <= temp; --在闸门的下降沿将数据读出
       end if;
end process p2;
end data;