counter.vhd

一些很好的FPGA设计实例

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all;
entity counter is
port(
      clk  :  in std_logic;
      sig  :  in std_logic;
      sig1 :  in std_logic; --０．５Ｈｚ的闸门信号，可由晶振分频得到
      read,read1: in std_logic;
      fcounter: out std_logic_vector (12 downto 0);
      dcounter : out std_logic_vector (12 downto 0)
     );        --计数输出
end counter;

architecture data of counter is
signal  temp : std_logic_vector(12 downto 0) ;
signal  temp1 : std_logic_vector(12 downto 0) ;
begin 
p1 : process(sig,clk)
     begin
       if clk'event and clk = '1' then 
          if sig = '1' then
          temp <= temp + 1; --在闸门的高电平时段计数
          else 
          temp <= (others=>'0') ;--在闸门的低电平时段清零
          end if;
        end if;
end process p1;

p2 : process(sig,read,temp)
       begin
         if read= '1' then
         if sig'event and sig = '0' then

          fcounter <= temp; --在闸门的下降沿将数据读出
         else
          temp <= temp;
         end if;
       end if;
end process p2;



p3 : process(sig1,clk)
     begin
       if clk'event and clk = '1' then 
          if sig1 = '1' then
          temp1 <= temp1 + 1; --在闸门的高电平时段计数
          else 
          temp1 <= (others=>'0') ;--在闸门的低电平时段清零
          end if;
        end if;
end process p3;

p4 : process(sig1,read1,temp1)
       begin
         if read1 = '1' then
         if sig1'event and sig1 = '0' then

         dcounter <= temp1; --在闸门的下降沿将数据读出
         else
          temp1 <= temp1;
         end if;
       end if;
end process p4;

end data;