data.vhd

一些很好的FPGA设计实例

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity  data is
port (
      sele:in std_logic;
      dcounter: in std_logic_vector(12 downto 0);
      fcounter: in std_logic_vector(12 downto 0);
      data  :  out std_logic_vector(12 downto 0)
     );
end data;
architecture data of data is
begin 
   with sele select
   data  <= fcounter  when  '0',
            dcounter  when  '1',
           "0000000000000" when others;
end data;