clkdiv.vhd

来自「一些很好的FPGA设计实例」· VHDL 代码 · 共 31 行

LIBRARY  IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY  clkdiv  IS
         PORT(
              clk        : IN STD_LOGIC;
             clk_div2    : OUT STD_LOGIC
              );
END clkdiv;

ARCHITECTURE rtl OF clkdiv IS
      SIGNAL  count : STD_LOGIC;
BEGIN
      PROCESS(clk)
      BEGIN
         IF(CLK'EVENT AND CLK = '1') THEN
             IF(count='1')THEN
              COUNT <= '0';
            ELSE
              Count <= count +'1';
            END IF ;
         END IF ;
  END PROCESS;

      clk_div2 <= count(1);

END rtl;