ddiv.vhd

来自「一些很好的FPGA设计实例」· VHDL 代码 · 共 19 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ddiv is
port ( clki : in std_logic;
       clko : out std_logic
     );
end ddiv;
architecture behave of ddiv is
SIGNAL temp : STD_LOGIC;
begin 
process (clki)
   begin
     if clki'event and clki='1' then
          TEMP <= NOT TEMP;
     end if;
end process;
CLKO <= TEMP;
end behave;