main.tan.qmsg

一些很好的FPGA设计实例

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clock_8MHz register fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[12\] register fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[22\] 192.31 MHz 5.2 ns Internal " "Info: Clock \"Clock_8MHz\" has Internal fmax of 192.31 MHz between source register \"fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[12\]\" and destination register \"fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[22\]\" (period= 5.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.500 ns + Longest register register " "Info: + Longest register to register delay is 4.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[12\] 1 REG LC6_B3 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_B3; Fanout = 3; REG Node = 'fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[12\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[12] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(0.700 ns) 1.200 ns fdiv:inst\|CNT~273 2 COMB LC3_B2 1 " "Info: 2: + IC(0.500 ns) + CELL(0.700 ns) = 1.200 ns; Loc. = LC3_B2; Fanout = 1; COMB Node = 'fdiv:inst\|CNT~273'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.200 ns" { fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[12] fdiv:inst|CNT~273 } "NODE_NAME" } } { "fdiv.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/fdiv.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 2.200 ns fdiv:inst\|CNT~266 3 COMB LC4_B2 1 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 2.200 ns; Loc. = LC4_B2; Fanout = 1; COMB Node = 'fdiv:inst\|CNT~266'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.000 ns" { fdiv:inst|CNT~273 fdiv:inst|CNT~266 } "NODE_NAME" } } { "fdiv.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/fdiv.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.000 ns) 3.300 ns fdiv:inst\|CNT~255 4 COMB LC1_B2 26 " "Info: 4: + IC(0.100 ns) + CELL(1.000 ns) = 3.300 ns; Loc. = LC1_B2; Fanout = 26; COMB Node = 'fdiv:inst\|CNT~255'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.100 ns" { fdiv:inst|CNT~266 fdiv:inst|CNT~255 } "NODE_NAME" } } { "fdiv.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/fdiv.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.600 ns) 4.500 ns fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[22\] 5 REG LC8_B5 2 " "Info: 5: + IC(0.600 ns) + CELL(0.600 ns) = 4.500 ns; Loc. = LC8_B5; Fanout = 2; REG Node = 'fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[22\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.200 ns" { fdiv:inst|CNT~255 fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[22] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.300 ns ( 73.33 % ) " "Info: Total cell delay = 3.300 ns ( 73.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns ( 26.67 % ) " "Info: Total interconnect delay = 1.200 ns ( 26.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.500 ns" { fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[12] fdiv:inst|CNT~273 fdiv:inst|CNT~266 fdiv:inst|CNT~255 fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[22] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.500 ns" { fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[12] fdiv:inst|CNT~273 fdiv:inst|CNT~266 fdiv:inst|CNT~255 fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[22] } { 0.000ns 0.500ns 0.000ns 0.100ns 0.600ns } { 0.000ns 0.700ns 1.000ns 1.000ns 0.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_8MHz destination 1.500 ns + Shortest register " "Info: + Shortest clock path from clock \"Clock_8MHz\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Clock_8MHz 1 CLK PIN_39 26 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 26; CLK Node = 'Clock_8MHz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Clock_8MHz } "NODE_NAME" } } { "main.bdf" "" { Schematic "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/main.bdf" { { 248 -200 -32 264 "Clock_8MHz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[22\] 2 REG LC8_B5 2 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC8_B5; Fanout = 2; REG Node = 'fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[22\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.200 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[22] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns ( 86.67 % ) " "Info: Total cell delay = 1.300 ns ( 86.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns ( 13.33 % ) " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[22] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { Clock_8MHz Clock_8MHz~out fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[22] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_8MHz source 1.500 ns - Longest register " "Info: - Longest clock path from clock \"Clock_8MHz\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Clock_8MHz 1 CLK PIN_39 26 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 26; CLK Node = 'Clock_8MHz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Clock_8MHz } "NODE_NAME" } } { "main.bdf" "" { Schematic "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/main.bdf" { { 248 -200 -32 264 "Clock_8MHz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[12\] 2 REG LC6_B3 3 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC6_B3; Fanout = 3; REG Node = 'fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[12\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.200 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[12] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns ( 86.67 % ) " "Info: Total cell delay = 1.300 ns ( 86.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns ( 13.33 % ) " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { Clock_8MHz Clock_8MHz~out fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[12] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[22] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { Clock_8MHz Clock_8MHz~out fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[22] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { Clock_8MHz Clock_8MHz~out fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[12] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns + " "Info: + Micro clock to output delay of source is 0.300 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.400 ns + " "Info: + Micro setup delay of destination is 0.400 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.500 ns" { fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[12] fdiv:inst|CNT~273 fdiv:inst|CNT~266 fdiv:inst|CNT~255 fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[22] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.500 ns" { fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[12] fdiv:inst|CNT~273 fdiv:inst|CNT~266 fdiv:inst|CNT~255 fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[22] } { 0.000ns 0.500ns 0.000ns 0.100ns 0.600ns } { 0.000ns 0.700ns 1.000ns 1.000ns 0.600ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[22] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { Clock_8MHz Clock_8MHz~out fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[22] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { Clock_8MHz Clock_8MHz~out fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[12] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "Reset 201 " "Warning: Circuit may not operate. Detected 201 non-operational path(s) clocked by clock \"Reset\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[15\] sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[15\] Reset 3.5 ns " "Info: Found hold time violation between source  pin or register \"sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[15\]\" and destination pin or register \"sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[15\]\" for clock \"Reset\" (Hold time is 3.5 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.700 ns + Largest " "Info: + Largest clock skew is 3.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Reset destination 8.300 ns + Longest register " "Info: + Longest clock path from clock \"Reset\" to destination register is 8.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Reset 1 CLK PIN_89 36 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_89; Fanout = 36; CLK Node = 'Reset'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Reset } "NODE_NAME" } } { "main.bdf" "" { Schematic "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/main.bdf" { { 112 -200 -32 128 "Reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 2.300 ns pulse_sum:inst4\|pulse_1\[3\] 2 REG LC5_C10 1 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 2.300 ns; Loc. = LC5_C10; Fanout = 1; REG Node = 'pulse_sum:inst4\|pulse_1\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.000 ns" { Reset pulse_sum:inst4|pulse_1[3] } "NODE_NAME" } } { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.100 ns) 3.500 ns pulse_sum:inst4\|pulse_out~125 3 COMB LC1_C10 1 " "Info: 3: + IC(0.100 ns) + CELL(1.100 ns) = 3.500 ns; Loc. = LC1_C10; Fanout = 1; COMB Node = 'pulse_sum:inst4\|pulse_out~125'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.200 ns" { pulse_sum:inst4|pulse_1[3] pulse_sum:inst4|pulse_out~125 } "NODE_NAME" } } { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.800 ns) 5.100 ns pulse_sum:inst4\|pulse_out~126 4 COMB LC2_C11 2 " "Info: 4: + IC(0.800 ns) + CELL(0.800 ns) = 5.100 ns; Loc. = LC2_C11; Fanout = 2; COMB Node = 'pulse_sum:inst4\|pulse_out~126'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.600 ns" { pulse_sum:inst4|pulse_out~125 pulse_sum:inst4|pulse_out~126 } "NODE_NAME" } } { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.800 ns) 6.000 ns pulse_sum:inst4\|pulse_out~128 5 COMB LC1_C11 28 " "Info: 5: + IC(0.100 ns) + CELL(0.800 ns) = 6.000 ns; Loc. = LC1_C11; Fanout = 28; COMB Node = 'pulse_sum:inst4\|pulse_out~128'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~128 } "NODE_NAME" } } { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(0.000 ns) 8.300 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[15\] 6 REG LC8_B20 5 " "Info: 6: + IC(2.300 ns) + CELL(0.000 ns) = 8.300 ns; Loc. = LC8_B20; Fanout = 5; REG Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[15\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.300 ns" { pulse_sum:inst4|pulse_out~128 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 60.24 % ) " "Info: Total cell delay = 5.000 ns ( 60.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns ( 39.76 % ) " "Info: Total interconnect delay = 3.300 ns ( 39.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.300 ns" { Reset pulse_sum:inst4|pulse_1[3] pulse_sum:inst4|pulse_out~125 pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~128 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.300 ns" { Reset Reset~out pulse_sum:inst4|pulse_1[3] pulse_sum:inst4|pulse_out~125 pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~128 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] } { 0.000ns 0.000ns 0.000ns 0.100ns 0.800ns 0.100ns 2.300ns } { 0.000ns 1.300ns 1.000ns 1.100ns 0.800ns 0.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Reset source 4.600 ns - Shortest register " "Info: - Shortest clock path from clock \"Reset\" to source register is 4.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Reset 1 CLK PIN_89 36 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_89; Fanout = 36; CLK Node = 'Reset'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Reset } "NODE_NAME" } } { "main.bdf" "" { Schematic "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/main.bdf" { { 112 -200 -32 128 "Reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 2.300 ns pulse_sum:inst4\|pulse_out~128 2 COMB LC1_C11 28 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 2.300 ns; Loc. = LC1_C11; Fanout = 28; COMB Node = 'pulse_sum:inst4\|pulse_out~128'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.000 ns" { Reset pulse_sum:inst4|pulse_out~128 } "NODE_NAME" } } { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(0.000 ns) 4.600 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[15\] 3 REG LC8_B20 5 " "Info: 3: + IC(2.300 ns) + CELL(0.000 ns) = 4.600 ns; Loc. = LC8_B20; Fanout = 5; REG Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[15\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.300 ns" { pulse_sum:inst4|pulse_out~128 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.300 ns ( 50.00 % ) " "Info: Total cell delay = 2.300 ns ( 50.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns ( 50.00 % ) " "Info: Total interconnect delay = 2.300 ns ( 50.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.600 ns" { Reset pulse_sum:inst4|pulse_out~128 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.600 ns" { Reset Reset~out pulse_sum:inst4|pulse_out~128 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] } { 0.000ns 0.000ns 0.000ns 2.300ns } { 0.000ns 1.300ns 1.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.300 ns" { Reset pulse_sum:inst4|pulse_1[3] pulse_sum:inst4|pulse_out~125 pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~128 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.300 ns" { Reset Reset~out pulse_sum:inst4|pulse_1[3] pulse_sum:inst4|pulse_out~125 pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~128 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] } { 0.000ns 0.000ns 0.000ns 0.100ns 0.800ns 0.100ns 2.300ns } { 0.000ns 1.300ns 1.000ns 1.100ns 0.800ns 0.800ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.600 ns" { Reset pulse_sum:inst4|pulse_out~128 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.600 ns" { Reset Reset~out pulse_sum:inst4|pulse_out~128 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] } { 0.000ns 0.000ns 0.000ns 2.300ns } { 0.000ns 1.300ns 1.000ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns - " "Info: - Micro clock to output delay of source is 0.300 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.600 ns - Shortest register register " "Info: - Shortest register to register delay is 0.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[15\] 1 REG LC8_B20 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_B20; Fanout = 5; REG Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[15\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 0.600 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[15\] 2 REG LC8_B20 5 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 0.600 ns; Loc. = LC8_B20; Fanout = 5; REG Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[15\]'" {  }