main.tan.qmsg

一些很好的FPGA设计实例

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Reset " "Info: Assuming node \"Reset\" is an undefined clock" {  } { { "main.bdf" "" { Schematic "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/main.bdf" { { 112 -200 -32 128 "Reset" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Reset" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "Clock_8MHz " "Info: Assuming node \"Clock_8MHz\" is an undefined clock" {  } { { "main.bdf" "" { Schematic "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/main.bdf" { { 248 -200 -32 264 "Clock_8MHz" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Clock_8MHz" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "22 " "Warning: Found 22 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "pulse_sum:inst4\|pulse_1\[10\] " "Info: Detected ripple clock \"pulse_sum:inst4\|pulse_1\[10\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[10\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "pulse_sum:inst4\|pulse_1\[9\] " "Info: Detected ripple clock \"pulse_sum:inst4\|pulse_1\[9\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[9\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "pulse_sum:inst4\|pulse_1\[8\] " "Info: Detected ripple clock \"pulse_sum:inst4\|pulse_1\[8\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[8\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "pulse_sum:inst4\|pulse_1\[7\] " "Info: Detected ripple clock \"pulse_sum:inst4\|pulse_1\[7\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "pulse_sum:inst4\|pulse_1\[14\] " "Info: Detected ripple clock \"pulse_sum:inst4\|pulse_1\[14\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[14\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "pulse_sum:inst4\|pulse_1\[13\] " "Info: Detected ripple clock \"pulse_sum:inst4\|pulse_1\[13\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[13\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "pulse_sum:inst4\|pulse_1\[12\] " "Info: Detected ripple clock \"pulse_sum:inst4\|pulse_1\[12\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[12\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "pulse_sum:inst4\|pulse_1\[11\] " "Info: Detected ripple clock \"pulse_sum:inst4\|pulse_1\[11\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[11\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "pulse_sum:inst4\|pulse_1\[2\] " "Info: Detected ripple clock \"pulse_sum:inst4\|pulse_1\[2\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "pulse_sum:inst4\|pulse_1\[1\] " "Info: Detected ripple clock \"pulse_sum:inst4\|pulse_1\[1\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "pulse_sum:inst4\|pulse_1\[0\] " "Info: Detected ripple clock \"pulse_sum:inst4\|pulse_1\[0\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "pulse_sum:inst4\|pulse_1\[6\] " "Info: Detected ripple clock \"pulse_sum:inst4\|pulse_1\[6\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "pulse_sum:inst4\|pulse_1\[5\] " "Info: Detected ripple clock \"pulse_sum:inst4\|pulse_1\[5\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "pulse_sum:inst4\|pulse_1\[4\] " "Info: Detected ripple clock \"pulse_sum:inst4\|pulse_1\[4\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "pulse_sum:inst4\|pulse_1\[3\] " "Info: Detected ripple clock \"pulse_sum:inst4\|pulse_1\[3\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\] " "Info: Detected ripple clock \"fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\]\" as buffer" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\] " "Info: Detected ripple clock \"fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\]\" as buffer" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_out~140 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_out~140\" as buffer" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 9 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_out~140" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_out~134 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_out~134\" as buffer" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 9 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_out~134" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_out~126 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_out~126\" as buffer" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 9 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_out~126" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_out~125 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_out~125\" as buffer" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 9 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_out~125" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_out~128 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_out~128\" as buffer" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 9 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_out~128" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Reset register sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] register sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 93.46 MHz 10.7 ns Internal " "Info: Clock \"Reset\" has Internal fmax of 93.46 MHz between source register \"sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]\" and destination register \"sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]\" (period= 10.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.300 ns + Longest register register " "Info: + Longest register to register delay is 6.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 1 REG LC4_B18 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_B18; Fanout = 4; REG Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(0.700 ns) 1.200 ns sum_control:inst5\|Equal0~344 2 COMB LC6_B24 1 " "Info: 2: + IC(0.500 ns) + CELL(0.700 ns) = 1.200 ns; Loc. = LC6_B24; Fanout = 1; COMB Node = 'sum_control:inst5\|Equal0~344'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.200 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] sum_control:inst5|Equal0~344 } "NODE_NAME" } } { "sum_control.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/sum_control.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 2.200 ns sum_control:inst5\|Equal0~320 3 COMB LC7_B24 1 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 2.200 ns; Loc. = LC7_B24; Fanout = 1; COMB Node = 'sum_control:inst5\|Equal0~320'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.000 ns" { sum_control:inst5|Equal0~344 sum_control:inst5|Equal0~320 } "NODE_NAME" } } { "sum_control.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/sum_control.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(1.100 ns) 3.800 ns sum_control:inst5\|Equal0~284 4 COMB LC6_B21 2 " "Info: 4: + IC(0.500 ns) + CELL(1.100 ns) = 3.800 ns; Loc. = LC6_B21; Fanout = 2; COMB Node = 'sum_control:inst5\|Equal0~284'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.600 ns" { sum_control:inst5|Equal0~320 sum_control:inst5|Equal0~284 } "NODE_NAME" } } { "sum_control.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/sum_control.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.100 ns) 5.000 ns sum_control:inst5\|step_counter\[22\]~965 5 COMB LC7_B21 54 " "Info: 5: + IC(0.100 ns) + CELL(1.100 ns) = 5.000 ns; Loc. = LC7_B21; Fanout = 54; COMB Node = 'sum_control:inst5\|step_counter\[22\]~965'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.200 ns" { sum_control:inst5|Equal0~284 sum_control:inst5|step_counter[22]~965 } "NODE_NAME" } } { "sum_control.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/sum_control.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.700 ns) 6.300 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 6 REG LC8_B18 4 " "Info: 6: + IC(0.600 ns) + CELL(0.700 ns) = 6.300 ns; Loc. = LC8_B18; Fanout = 4; REG Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.300 ns" { sum_control:inst5|step_counter[22]~965 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns ( 73.02 % ) " "Info: Total cell delay = 4.600 ns ( 73.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns ( 26.98 % ) " "Info: Total interconnect delay = 1.700 ns ( 26.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.300 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] sum_control:inst5|Equal0~344 sum_control:inst5|Equal0~320 sum_control:inst5|Equal0~284 sum_control:inst5|step_counter[22]~965 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.300 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] sum_control:inst5|Equal0~344 sum_control:inst5|Equal0~320 sum_control:inst5|Equal0~284 sum_control:inst5|step_counter[22]~965 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 0.500ns 0.000ns 0.500ns 0.100ns 0.600ns } { 0.000ns 0.700ns 1.000ns 1.100ns 1.100ns 0.700ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.700 ns - Smallest " "Info: - Smallest clock skew is -3.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Reset destination 4.600 ns + Shortest register " "Info: + Shortest clock path from clock \"Reset\" to destination register is 4.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Reset 1 CLK PIN_89 36 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_89; Fanout = 36; CLK Node = 'Reset'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Reset } "NODE_NAME" } } { "main.bdf" "" { Schematic "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/main.bdf" { { 112 -200 -32 128 "Reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 2.300 ns pulse_sum:inst4\|pulse_out~128 2 COMB LC1_C11 28 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 2.300 ns; Loc. = LC1_C11; Fanout = 28; COMB Node = 'pulse_sum:inst4\|pulse_out~128'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.000 ns" { Reset pulse_sum:inst4|pulse_out~128 } "NODE_NAME" } } { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(0.000 ns) 4.600 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 3 REG LC8_B18 4 " "Info: 3: + IC(2.300 ns) + CELL(0.000 ns) = 4.600 ns; Loc. = LC8_B18; Fanout = 4; REG Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.300 ns" { pulse_sum:inst4|pulse_out~128 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.300 ns ( 50.00 % ) " "Info: Total cell delay = 2.300 ns ( 50.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns ( 50.00 % ) " "Info: Total interconnect delay = 2.300 ns ( 50.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.600 ns" { Reset pulse_sum:inst4|pulse_out~128 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.600 ns" { Reset Reset~out pulse_sum:inst4|pulse_out~128 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 0.000ns 0.000ns 2.300ns } { 0.000ns 1.300ns 1.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Reset source 8.300 ns - Longest register " "Info: - Longest clock path from clock \"Reset\" to source register is 8.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Reset 1 CLK PIN_89 36 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_89; Fanout = 36; CLK Node = 'Reset'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Reset } "NODE_NAME" } } { "main.bdf" "" { Schematic "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/main.bdf" { { 112 -200 -32 128 "Reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 2.300 ns pulse_sum:inst4\|pulse_1\[3\] 2 REG LC5_C10 1 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 2.300 ns; Loc. = LC5_C10; Fanout = 1; REG Node = 'pulse_sum:inst4\|pulse_1\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.000 ns" { Reset pulse_sum:inst4|pulse_1[3] } "NODE_NAME" } } { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.100 ns) 3.500 ns pulse_sum:inst4\|pulse_out~125 3 COMB LC1_C10 1 " "Info: 3: + IC(0.100 ns) + CELL(1.100 ns) = 3.500 ns; Loc. = LC1_C10; Fanout = 1; COMB Node = 'pulse_sum:inst4\|pulse_out~125'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.200 ns" { pulse_sum:inst4|pulse_1[3] pulse_sum:inst4|pulse_out~125 } "NODE_NAME" } } { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.800 ns) 5.100 ns pulse_sum:inst4\|pulse_out~126 4 COMB LC2_C11 2 " "Info: 4: + IC(0.800 ns) + CELL(0.800 ns) = 5.100 ns; Loc. = LC2_C11; Fanout = 2; COMB Node = 'pulse_sum:inst4\|pulse_out~126'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.600 ns" { pulse_sum:inst4|pulse_out~125 pulse_sum:inst4|pulse_out~126 } "NODE_NAME" } } { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.800 ns) 6.000 ns pulse_sum:inst4\|pulse_out~128 5 COMB LC1_C11 28 " "Info: 5: + IC(0.100 ns) + CELL(0.800 ns) = 6.000 ns; Loc. = LC1_C11; Fanout = 28; COMB Node = 'pulse_sum:inst4\|pulse_out~128'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~128 } "NODE_NAME" } } { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(0.000 ns) 8.300 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 6 REG LC4_B18 4 " "Info: 6: + IC(2.300 ns) + CELL(0.000 ns) = 8.300 ns; Loc. = LC4_B18; Fanout = 4; REG Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.300 ns" { pulse_sum:inst4|pulse_out~128 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 60.24 % ) " "Info: Total cell delay = 5.000 ns ( 60.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns ( 39.76 % ) " "Info: Total interconnect delay = 3.300 ns ( 39.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.300 ns" { Reset pulse_sum:inst4|pulse_1[3] pulse_sum:inst4|pulse_out~125 pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~128 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.300 ns" { Reset Reset~out pulse_sum:inst4|pulse_1[3] pulse_sum:inst4|pulse_out~125 pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~128 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 0.000ns 0.100ns 0.800ns 0.100ns 2.300ns } { 0.000ns 1.300ns 1.000ns 1.100ns 0.800ns 0.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.600 ns" { Reset pulse_sum:inst4|pulse_out~128 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.600 ns" { Reset Reset~out pulse_sum:inst4|pulse_out~128 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 0.000ns 0.000ns 2.300ns } { 0.000ns 1.300ns 1.000ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.300 ns" { Reset pulse_sum:inst4|pulse_1[3] pulse_sum:inst4|pulse_out~125 pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~128 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.300 ns" { Reset Reset~out pulse_sum:inst4|pulse_1[3] pulse_sum:inst4|pulse_out~125 pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~128 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 0.000ns 0.100ns 0.800ns 0.100ns 2.300ns } { 0.000ns 1.300ns 1.000ns 1.100ns 0.800ns 0.800ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns + " "Info: + Micro clock to output delay of source is 0.300 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.400 ns + " "Info: + Micro setup delay of destination is 0.400 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.300 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] sum_control:inst5|Equal0~344 sum_control:inst5|Equal0~320 sum_control:inst5|Equal0~284 sum_control:inst5|step_counter[22]~965 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.300 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] sum_control:inst5|Equal0~344 sum_control:inst5|Equal0~320 sum_control:inst5|Equal0~284 sum_control:inst5|step_counter[22]~965 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 0.500ns 0.000ns 0.500ns 0.100ns 0.600ns } { 0.000ns 0.700ns 1.000ns 1.100ns 1.100ns 0.700ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.600 ns" { Reset pulse_sum:inst4|pulse_out~128 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.600 ns" { Reset Reset~out pulse_sum:inst4|pulse_out~128 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 0.000ns 0.000ns 2.300ns } { 0.000ns 1.300ns 1.000ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.300 ns" { Reset pulse_sum:inst4|pulse_1[3] pulse_sum:inst4|pulse_out~125 pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~128 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.300 ns" { Reset Reset~out pulse_sum:inst4|pulse_1[3] pulse_sum:inst4|pulse_out~125 pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~128 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 0.000ns 0.100ns 0.800ns 0.100ns 2.300ns } { 0.000ns 1.300ns 1.000ns 1.100ns 0.800ns 0.800ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}