main.hier_info

一些很好的FPGA设计实例

|main
Pulse_Wave <= sum_control:inst5.wave_out
Reset => sum_control:inst5.Reset
Reset => pulse_sum:inst4.Reset
Reset => fdiv:inst.Reset
Reset => pulse_16:inst2.Reset
Reset => counter_16_bits:inst1.Reset
Reset => second_pulse_latch:inst3.Reset
Clock_8MHz => fdiv:inst.Clock_8MHz
Acceleration[0] => second_pulse_latch:inst3.acceleration[0]
Acceleration[1] => second_pulse_latch:inst3.acceleration[1]
Acceleration[2] => second_pulse_latch:inst3.acceleration[2]
Acceleration[3] => second_pulse_latch:inst3.acceleration[3]
Acceleration[4] => second_pulse_latch:inst3.acceleration[4]
Acceleration[5] => second_pulse_latch:inst3.acceleration[5]
Acceleration[6] => second_pulse_latch:inst3.acceleration[6]
Acceleration[7] => second_pulse_latch:inst3.acceleration[7]
Acceleration[8] => second_pulse_latch:inst3.acceleration[8]
Acceleration[9] => second_pulse_latch:inst3.acceleration[9]
Acceleration[10] => second_pulse_latch:inst3.acceleration[10]
Acceleration[11] => second_pulse_latch:inst3.acceleration[11]
Acceleration[12] => second_pulse_latch:inst3.acceleration[12]
Acceleration[13] => second_pulse_latch:inst3.acceleration[13]
Acceleration[14] => second_pulse_latch:inst3.acceleration[14]
Acceleration[15] => second_pulse_latch:inst3.acceleration[15]
Acceleration[16] => second_pulse_latch:inst3.acceleration[16]
Initial_Speed[0] => second_pulse_latch:inst3.speed[0]
Initial_Speed[1] => second_pulse_latch:inst3.speed[1]
Initial_Speed[2] => second_pulse_latch:inst3.speed[2]
Initial_Speed[3] => second_pulse_latch:inst3.speed[3]
Initial_Speed[4] => second_pulse_latch:inst3.speed[4]
Initial_Speed[5] => second_pulse_latch:inst3.speed[5]
Initial_Speed[6] => second_pulse_latch:inst3.speed[6]
Initial_Speed[7] => second_pulse_latch:inst3.speed[7]
Initial_Speed[8] => second_pulse_latch:inst3.speed[8]
Initial_Speed[9] => second_pulse_latch:inst3.speed[9]
Initial_Speed[10] => second_pulse_latch:inst3.speed[10]
Initial_Speed[11] => second_pulse_latch:inst3.speed[11]
Initial_Speed[12] => second_pulse_latch:inst3.speed[12]
Initial_Speed[13] => second_pulse_latch:inst3.speed[13]
Initial_Speed[14] => second_pulse_latch:inst3.speed[14]
Initial_Speed[15] => second_pulse_latch:inst3.speed[15]
Step_Sum[0] => sum_control:inst5.step_sum[0]
Step_Sum[1] => sum_control:inst5.step_sum[1]
Step_Sum[2] => sum_control:inst5.step_sum[2]
Step_Sum[3] => sum_control:inst5.step_sum[3]
Step_Sum[4] => sum_control:inst5.step_sum[4]
Step_Sum[5] => sum_control:inst5.step_sum[5]
Step_Sum[6] => sum_control:inst5.step_sum[6]
Step_Sum[7] => sum_control:inst5.step_sum[7]
Step_Sum[8] => sum_control:inst5.step_sum[8]
Step_Sum[9] => sum_control:inst5.step_sum[9]
Step_Sum[10] => sum_control:inst5.step_sum[10]
Step_Sum[11] => sum_control:inst5.step_sum[11]
Step_Sum[12] => sum_control:inst5.step_sum[12]
Step_Sum[13] => sum_control:inst5.step_sum[13]
Step_Sum[14] => sum_control:inst5.step_sum[14]
Step_Sum[15] => sum_control:inst5.step_sum[15]
Step_Sum[16] => sum_control:inst5.step_sum[16]
Step_Sum[17] => sum_control:inst5.step_sum[17]
Step_Sum[18] => sum_control:inst5.step_sum[18]
Step_Sum[19] => sum_control:inst5.step_sum[19]
Step_Sum[20] => sum_control:inst5.step_sum[20]
Step_Sum[21] => sum_control:inst5.step_sum[21]
Step_Sum[22] => sum_control:inst5.step_sum[22]
Step_Sum[23] => sum_control:inst5.step_sum[23]


|main|sum_control:inst5
Reset => step_counter~48.OUTPUTSELECT
Reset => step_counter~49.OUTPUTSELECT
Reset => step_counter~50.OUTPUTSELECT
Reset => step_counter~51.OUTPUTSELECT
Reset => step_counter~52.OUTPUTSELECT
Reset => step_counter~53.OUTPUTSELECT
Reset => step_counter~54.OUTPUTSELECT
Reset => step_counter~55.OUTPUTSELECT
Reset => step_counter~56.OUTPUTSELECT
Reset => step_counter~57.OUTPUTSELECT
Reset => step_counter~58.OUTPUTSELECT
Reset => step_counter~59.OUTPUTSELECT
Reset => step_counter~60.OUTPUTSELECT
Reset => step_counter~61.OUTPUTSELECT
Reset => step_counter~62.OUTPUTSELECT
Reset => step_counter~63.OUTPUTSELECT
Reset => step_counter~64.OUTPUTSELECT
Reset => step_counter~65.OUTPUTSELECT
Reset => step_counter~66.OUTPUTSELECT
Reset => step_counter~67.OUTPUTSELECT
Reset => step_counter~68.OUTPUTSELECT
Reset => step_counter~69.OUTPUTSELECT
Reset => step_counter~70.OUTPUTSELECT
Reset => step_counter~71.OUTPUTSELECT
Reset => out_control~2.OUTPUTSELECT
pulse_sum_in => step_counter[22].CLK
pulse_sum_in => step_counter[21].CLK
pulse_sum_in => step_counter[20].CLK
pulse_sum_in => step_counter[19].CLK
pulse_sum_in => step_counter[18].CLK
pulse_sum_in => step_counter[17].CLK
pulse_sum_in => step_counter[16].CLK
pulse_sum_in => step_counter[15].CLK
pulse_sum_in => step_counter[14].CLK
pulse_sum_in => step_counter[13].CLK
pulse_sum_in => step_counter[12].CLK
pulse_sum_in => step_counter[11].CLK
pulse_sum_in => step_counter[10].CLK
pulse_sum_in => step_counter[9].CLK
pulse_sum_in => step_counter[8].CLK
pulse_sum_in => step_counter[7].CLK
pulse_sum_in => step_counter[6].CLK
pulse_sum_in => step_counter[5].CLK
pulse_sum_in => step_counter[4].CLK
pulse_sum_in => step_counter[3].CLK
pulse_sum_in => step_counter[2].CLK
pulse_sum_in => step_counter[1].CLK
pulse_sum_in => step_counter[0].CLK
pulse_sum_in => out_control.CLK
pulse_sum_in => wave_out~0.IN1
pulse_sum_in => step_counter[23].CLK
step_sum[0] => Add0.IN48
step_sum[1] => Add0.IN47
step_sum[2] => Add0.IN46
step_sum[3] => Add0.IN45
step_sum[4] => Add0.IN44
step_sum[5] => Add0.IN43
step_sum[6] => Add0.IN42
step_sum[7] => Add0.IN41
step_sum[8] => Add0.IN40
step_sum[9] => Add0.IN39
step_sum[10] => Add0.IN38
step_sum[11] => Add0.IN37
step_sum[12] => Add0.IN36
step_sum[13] => Add0.IN35
step_sum[14] => Add0.IN34
step_sum[15] => Add0.IN33
step_sum[16] => Add0.IN32
step_sum[17] => Add0.IN31
step_sum[18] => Add0.IN30
step_sum[19] => Add0.IN29
step_sum[20] => Add0.IN28
step_sum[21] => Add0.IN27
step_sum[22] => Add0.IN26
step_sum[23] => Add0.IN25
wave_out <= wave_out~0.DB_MAX_OUTPUT_PORT_TYPE


|main|pulse_sum:inst4
Reset => pulse_out~14.OUTPUTSELECT
Reset => pulse_1[13].LATCH_ENABLE
Reset => pulse_1[14].LATCH_ENABLE
Reset => pulse_1[12].LATCH_ENABLE
Reset => pulse_1[11].LATCH_ENABLE
Reset => pulse_1[10].LATCH_ENABLE
Reset => pulse_1[9].LATCH_ENABLE
Reset => pulse_1[8].LATCH_ENABLE
Reset => pulse_1[7].LATCH_ENABLE
Reset => pulse_1[6].LATCH_ENABLE
Reset => pulse_1[5].LATCH_ENABLE
Reset => pulse_1[4].LATCH_ENABLE
Reset => pulse_1[3].LATCH_ENABLE
Reset => pulse_1[2].LATCH_ENABLE
Reset => pulse_1[1].LATCH_ENABLE
Reset => pulse_1[0].LATCH_ENABLE
Clock_65536Hz => pulse_1~1.IN0
Clock_65536Hz => pulse_1~3.IN0
Clock_65536Hz => pulse_1~5.IN0
Clock_65536Hz => pulse_1~7.IN0
Clock_65536Hz => pulse_1~9.IN0
Clock_65536Hz => pulse_1~11.IN0
Clock_65536Hz => pulse_1~13.IN0
Clock_65536Hz => pulse_1~15.IN0
Clock_65536Hz => pulse_1~17.IN0
Clock_65536Hz => pulse_1~19.IN0
Clock_65536Hz => pulse_1~21.IN0
Clock_65536Hz => pulse_1~23.IN0
Clock_65536Hz => pulse_1~25.IN0
Clock_65536Hz => pulse_1~27.IN0
Clock_65536Hz => pulse_1~29.IN1
pulse_16_data[0] => pulse_1~0.IN0
pulse_16_data[1] => pulse_1~2.IN0
pulse_16_data[2] => pulse_1~4.IN0
pulse_16_data[3] => pulse_1~6.IN0
pulse_16_data[4] => pulse_1~8.IN0
pulse_16_data[5] => pulse_1~10.IN0
pulse_16_data[6] => pulse_1~12.IN0
pulse_16_data[7] => pulse_1~14.IN0
pulse_16_data[8] => pulse_1~16.IN0
pulse_16_data[9] => pulse_1~18.IN0
pulse_16_data[10] => pulse_1~20.IN0
pulse_16_data[11] => pulse_1~22.IN0
pulse_16_data[12] => pulse_1~24.IN0
pulse_16_data[13] => pulse_1~26.IN0
pulse_16_data[14] => pulse_1~28.IN0
pulse_16_data[15] => ~NO_FANOUT~
second_pulse_data[0] => pulse_1~0.IN1
second_pulse_data[1] => pulse_1~2.IN1
second_pulse_data[2] => pulse_1~4.IN1
second_pulse_data[3] => pulse_1~6.IN1
second_pulse_data[4] => pulse_1~8.IN1
second_pulse_data[5] => pulse_1~10.IN1
second_pulse_data[6] => pulse_1~12.IN1
second_pulse_data[7] => pulse_1~14.IN1
second_pulse_data[8] => pulse_1~16.IN1
second_pulse_data[9] => pulse_1~18.IN1
second_pulse_data[10] => pulse_1~20.IN1
second_pulse_data[11] => pulse_1~22.IN1
second_pulse_data[12] => pulse_1~24.IN1
second_pulse_data[13] => pulse_1~26.IN1
second_pulse_data[14] => pulse_1~28.IN1
second_pulse_data[15] => ~NO_FANOUT~
pulse_out <= pulse_out~14.DB_MAX_OUTPUT_PORT_TYPE


|main|fdiv:inst
Reset => CNT~23.OUTPUTSELECT
Reset => CNT~24.OUTPUTSELECT
Reset => CNT~25.OUTPUTSELECT
Reset => CNT~26.OUTPUTSELECT
Reset => CNT~27.OUTPUTSELECT
Reset => CNT~28.OUTPUTSELECT
Reset => CNT~29.OUTPUTSELECT
Reset => CNT~30.OUTPUTSELECT
Reset => CNT~31.OUTPUTSELECT
Reset => CNT~32.OUTPUTSELECT
Reset => CNT~33.OUTPUTSELECT
Reset => CNT~34.OUTPUTSELECT
Reset => CNT~35.OUTPUTSELECT
Reset => CNT~36.OUTPUTSELECT
Reset => CNT~37.OUTPUTSELECT
Reset => CNT~38.OUTPUTSELECT
Reset => CNT~39.OUTPUTSELECT
Reset => CNT~40.OUTPUTSELECT
Reset => CNT~41.OUTPUTSELECT
Reset => CNT~42.OUTPUTSELECT
Reset => CNT~43.OUTPUTSELECT
Reset => CNT~44.OUTPUTSELECT
Reset => CNT~45.OUTPUTSELECT
Clock_8MHz => CNT[21].CLK
Clock_8MHz => CNT[20].CLK
Clock_8MHz => CNT[19].CLK
Clock_8MHz => CNT[18].CLK
Clock_8MHz => CNT[17].CLK
Clock_8MHz => CNT[16].CLK
Clock_8MHz => CNT[15].CLK
Clock_8MHz => CNT[14].CLK
Clock_8MHz => CNT[13].CLK
Clock_8MHz => CNT[12].CLK
Clock_8MHz => CNT[11].CLK
Clock_8MHz => CNT[10].CLK
Clock_8MHz => CNT[9].CLK
Clock_8MHz => CNT[8].CLK
Clock_8MHz => CNT[7].CLK
Clock_8MHz => CNT[6].CLK
Clock_8MHz => CNT[5].CLK
Clock_8MHz => CNT[4].CLK
Clock_8MHz => CNT[3].CLK
Clock_8MHz => CNT[2].CLK
Clock_8MHz => CNT[1].CLK
Clock_8MHz => CNT[0].CLK
Clock_8MHz => CNT[22].CLK
F_65536Hz <= CNT[1].DB_MAX_OUTPUT_PORT_TYPE
F_1Hz <= CNT[3].DB_MAX_OUTPUT_PORT_TYPE


|main|pulse_16:inst2
Reset => pulse_16_out~0.OUTPUTSELECT
Reset => pulse_16_out~1.OUTPUTSELECT
Reset => pulse_16_out~2.OUTPUTSELECT
Reset => pulse_16_out~3.OUTPUTSELECT
Reset => pulse_16_out~4.OUTPUTSELECT
Reset => pulse_16_out~5.OUTPUTSELECT
Reset => pulse_16_out~6.OUTPUTSELECT
Reset => pulse_16_out~7.OUTPUTSELECT
Reset => pulse_16_out~8.OUTPUTSELECT
Reset => pulse_16_out~9.OUTPUTSELECT
Reset => pulse_16_out~10.OUTPUTSELECT
Reset => pulse_16_out~11.OUTPUTSELECT
Reset => pulse_16_out~12.OUTPUTSELECT
Reset => pulse_16_out~13.OUTPUTSELECT
Reset => pulse_16_out~14.OUTPUTSELECT
Reset => pulse_16_out~15.OUTPUTSELECT
counter_data[0] => pulse_16_out~0.DATAA
counter_data[0] => Equal0.IN0
counter_data[0] => Equal1.IN1
counter_data[0] => Equal2.IN2
counter_data[0] => Equal3.IN3
counter_data[0] => Equal4.IN4
counter_data[0] => Equal5.IN5
counter_data[0] => Equal6.IN6
counter_data[0] => Equal7.IN7
counter_data[0] => Equal8.IN8
counter_data[0] => Equal9.IN9
counter_data[0] => Equal10.IN10
counter_data[0] => Equal11.IN11
counter_data[0] => Equal12.IN12
counter_data[0] => Equal13.IN13
counter_data[0] => Equal14.IN14
counter_data[1] => Equal0.IN1
counter_data[1] => Equal1.IN0
counter_data[1] => Equal2.IN1
counter_data[1] => Equal3.IN2