main.map.qmsg

一些很好的FPGA设计实例

{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "pulse_1\[10\] pulse_sum.v(22) " "Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for \"pulse_1\[10\]\"" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "pulse_1\[9\] pulse_sum.v(22) " "Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for \"pulse_1\[9\]\"" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "pulse_1\[8\] pulse_sum.v(22) " "Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for \"pulse_1\[8\]\"" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "pulse_1\[7\] pulse_sum.v(22) " "Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for \"pulse_1\[7\]\"" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "pulse_1\[6\] pulse_sum.v(22) " "Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for \"pulse_1\[6\]\"" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "pulse_1\[5\] pulse_sum.v(22) " "Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for \"pulse_1\[5\]\"" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "pulse_1\[4\] pulse_sum.v(22) " "Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for \"pulse_1\[4\]\"" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "pulse_1\[3\] pulse_sum.v(22) " "Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for \"pulse_1\[3\]\"" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "pulse_1\[2\] pulse_sum.v(22) " "Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for \"pulse_1\[2\]\"" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "pulse_1\[1\] pulse_sum.v(22) " "Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for \"pulse_1\[1\]\"" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "pulse_1\[0\] pulse_sum.v(22) " "Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for \"pulse_1\[0\]\"" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "pulse_1\[15\] 0 pulse_sum.v(17) " "Warning (10030): Tied undriven net \"pulse_1\[15\]\" at pulse_sum.v(17) to 0" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 17 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fdiv fdiv:inst " "Info: Elaborating entity \"fdiv\" for hierarchy \"fdiv:inst\"" {  } { { "main.bdf" "inst" { Schematic "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/main.bdf" { { 208 -16 152 304 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pulse_16 pulse_16:inst2 " "Info: Elaborating entity \"pulse_16\" for hierarchy \"pulse_16:inst2\"" {  } { { "main.bdf" "inst2" { Schematic "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/main.bdf" { { 128 432 680 224 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_16_bits counter_16_bits:inst1 " "Info: Elaborating entity \"counter_16_bits\" for hierarchy \"counter_16_bits:inst1\"" {  } { { "main.bdf" "inst1" { Schematic "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/main.bdf" { { 128 200 408 224 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "second_pulse_latch second_pulse_latch:inst3 " "Info: Elaborating entity \"second_pulse_latch\" for hierarchy \"second_pulse_latch:inst3\"" {  } { { "main.bdf" "inst3" { Schematic "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/main.bdf" { { 256 200 464 384 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_IGNORE_INIT" "second_pulse_latch.v(19) " "Warning (10101): Verilog HDL unsupported feature warning at second_pulse_latch.v(19): Initial Construct is not supported and will be ignored" {  } { { "second_pulse_latch.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/second_pulse_latch.v" 19 0 0 } }  } 0 10101 "Verilog HDL unsupported feature warning at %1!s!: Initial Construct is not supported and will be ignored" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "3 " "Info: Inferred 3 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "sum_control:inst5\|step_counter\[0\]~956 24 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=24) from the following logic: \"sum_control:inst5\|step_counter\[0\]~956\"" {  } { { "sum_control.v" "step_counter\[0\]~956" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/sum_control.v" 37 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "fdiv:inst\|CNT\[0\]~69 23 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=23) from the following logic: \"fdiv:inst\|CNT\[0\]~69\"" {  } { { "fdiv.v" "CNT\[0\]~69" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/fdiv.v" 27 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "counter_16_bits:inst1\|counter_out\[0\]~16 16 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: \"counter_16_bits:inst1\|counter_out\[0\]~16\"" {  } { { "counter_16_bits.v" "counter_out\[0\]~16" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/counter_16_bits.v" 17 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "sum_control:inst5\|lpm_counter:step_counter_rtl_0 " "Info: Elaborated megafunction instantiation \"sum_control:inst5\|lpm_counter:step_counter_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 250 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter sum_control:inst5\|lpm_counter:step_counter_rtl_0 " "Info: Elaborated megafunction instantiation \"sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\", which is child of megafunction instantiation \"sum_control:inst5\|lpm_counter:step_counter_rtl_0\"" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 417 4 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sum_control:inst5\|lpm_counter:step_counter_rtl_0 " "Info: Instantiated megafunction \"sum_control:inst5\|lpm_counter:step_counter_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 24 " "Info: Parameter \"LPM_WIDTH\" = \"24\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Info: Parameter \"LPM_DIRECTION\" = \"UP\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Info: Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}