main.map.qmsg

一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 26 19:42:40 2008 " "Info: Processing started: Mon May 26 19:42:40 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off main -c main " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off main -c main" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter_16_bits.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file counter_16_bits.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16_bits " "Info: Found entity 1: counter_16_bits" {  } { { "counter_16_bits.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/counter_16_bits.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fdiv.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fdiv.v" { { "Info" "ISGN_ENTITY_NAME" "1 fdiv " "Info: Found entity 1: fdiv" {  } { { "fdiv.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/fdiv.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pulse_16.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file pulse_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 pulse_16 " "Info: Found entity 1: pulse_16" {  } { { "pulse_16.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_16.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pulse_sum.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file pulse_sum.v" { { "Info" "ISGN_ENTITY_NAME" "1 pulse_sum " "Info: Found entity 1: pulse_sum" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "second_pulse_latch.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file second_pulse_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 second_pulse_latch " "Info: Found entity 1: second_pulse_latch" {  } { { "second_pulse_latch.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/second_pulse_latch.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sum_control.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sum_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 sum_control " "Info: Found entity 1: sum_control" {  } { { "sum_control.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/sum_control.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "main.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file main.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 main " "Info: Found entity 1: main" {  } { { "main.bdf" "" { Schematic "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/main.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "main " "Info: Elaborating entity \"main\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sum_control sum_control:inst5 " "Info: Elaborating entity \"sum_control\" for hierarchy \"sum_control:inst5\"" {  } { { "main.bdf" "inst5" { Schematic "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/main.bdf" { { 288 736 920 384 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pulse_sum pulse_sum:inst4 " "Info: Elaborating entity \"pulse_sum\" for hierarchy \"pulse_sum:inst4\"" {  } { { "main.bdf" "inst4" { Schematic "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/main.bdf" { { 96 712 936 224 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "cnt pulse_sum.v(20) " "Warning (10240): Verilog HDL Always Construct warning at pulse_sum.v(20): inferring latch(es) for variable \"cnt\", which holds its previous value in one or more paths through the always construct" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 20 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "cnt\[3\] pulse_sum.v(18) " "Info (10041): Verilog HDL or VHDL info at pulse_sum.v(18): inferred latch for \"cnt\[3\]\"" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 18 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "cnt\[2\] pulse_sum.v(18) " "Info (10041): Verilog HDL or VHDL info at pulse_sum.v(18): inferred latch for \"cnt\[2\]\"" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 18 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "cnt\[1\] pulse_sum.v(18) " "Info (10041): Verilog HDL or VHDL info at pulse_sum.v(18): inferred latch for \"cnt\[1\]\"" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 18 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "cnt\[0\] pulse_sum.v(18) " "Info (10041): Verilog HDL or VHDL info at pulse_sum.v(18): inferred latch for \"cnt\[0\]\"" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 18 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "pulse_1 pulse_sum.v(20) " "Warning (10240): Verilog HDL Always Construct warning at pulse_sum.v(20): inferring latch(es) for variable \"pulse_1\", which holds its previous value in one or more paths through the always construct" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 20 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "pulse_1\[14\] pulse_sum.v(22) " "Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for \"pulse_1\[14\]\"" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "pulse_1\[13\] pulse_sum.v(22) " "Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for \"pulse_1\[13\]\"" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "pulse_1\[12\] pulse_sum.v(22) " "Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for \"pulse_1\[12\]\"" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "pulse_1\[11\] pulse_sum.v(22) " "Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for \"pulse_1\[11\]\"" {  } { { "pulse_sum.v" "" { Text "D:/整理资料/fpga/步进电机位置控制系统/第7章/main/pulse_sum.v" 22 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}