main.map.summary

来自「一些很好的FPGA设计实例」· SUMMARY 代码 · 共 10 行

Analysis & Synthesis Status : Successful - Mon May 26 19:42:49 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : main
Top-level Entity Name : main
Family : ACEX1K
Total logic elements : 211
Total pins : 60
Total memory bits : 0
Total PLLs : 0