pulse_sum.v

来自「一些很好的FPGA设计实例」· Verilog 代码 · 共 42 行

module pulse_sum(
                  Reset,
                  Clock_65536Hz,
                  pulse_16_data,
                  second_pulse_data,
                 // all_pulse_set,
                  pulse_out                  
                  );
output pulse_out;
input  Reset;
input  Clock_65536Hz;
input  [15:0] pulse_16_data;
input  [15:0] second_pulse_data;
//input  [23:0] all_pulse_set; //总脉冲数，用于走步距离的控制， 

reg pulse_out;
reg [15:0] pulse_1;
reg [3:0] cnt;

always @(Reset,Clock_65536Hz,pulse_16_data,second_pulse_data,pulse_1,cnt)
begin
  if(Reset == 1'b1)
    pulse_out <= 1'b0;
  else
  begin
    for(cnt = 4'b0;cnt < 4'b1111;cnt = cnt + 4'b1)
    begin
      pulse_1[cnt] <= second_pulse_data[cnt] && pulse_16_data[cnt] && Clock_65536Hz;
      //cnt <= cnt +4'b1;
      if(cnt == 4'b1111) cnt <= 4'b0;
    end
    pulse_out <= pulse_1[0] || pulse_1[1] ||
                 pulse_1[2] || pulse_1[3] ||
                 pulse_1[4] || pulse_1[5] ||
                 pulse_1[6] || pulse_1[7] ||
                 pulse_1[8] || pulse_1[9] ||
                 pulse_1[10] || pulse_1[11] ||
                 pulse_1[12] || pulse_1[13] ||
                 pulse_1[14] || pulse_1[15];
  end
end
endmodule