main.map.eqn

一些很好的FPGA设计实例

--J3_q[14] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14]
--operation mode is clrb_cntr

J3_q[14]_lut_out = (J3_q[14] $ (A1L04 & J3L92)) & A1L93;
J3_q[14] = DFFEA(J3_q[14]_lut_out, F1L93, , , A1L04, , );

--J3L13 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[14]~COUT
--operation mode is clrb_cntr

J3L13 = CARRY(J3_q[14] & J3L92);


--G1L4 is sum_control:inst5|out_control~238
--operation mode is normal

G1L4 = !J3_q[14] # !J3_q[1] # !J3_q[11] # !J3_q[12];


--J3_q[6] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]
--operation mode is clrb_cntr

J3_q[6]_lut_out = (J3_q[6] $ (A1L04 & J3L31)) & A1L93;
J3_q[6] = DFFEA(J3_q[6]_lut_out, F1L93, , , A1L04, , );

--J3L51 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT
--operation mode is clrb_cntr

J3L51 = CARRY(J3_q[6] & J3L31);


--J3_q[22] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22]
--operation mode is clrb_cntr

J3_q[22]_lut_out = (J3_q[22] $ (A1L04 & J3L54)) & A1L93;
J3_q[22] = DFFEA(J3_q[22]_lut_out, F1L93, , , A1L04, , );

--J3L74 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[22]~COUT
--operation mode is clrb_cntr

J3L74 = CARRY(J3_q[22] & J3L54);


--J3_q[10] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10]
--operation mode is clrb_cntr

J3_q[10]_lut_out = (J3_q[10] $ (A1L04 & J3L12)) & A1L93;
J3_q[10] = DFFEA(J3_q[10]_lut_out, F1L93, , , A1L04, , );

--J3L32 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[10]~COUT
--operation mode is clrb_cntr

J3L32 = CARRY(J3_q[10] & J3L12);


--J3_q[17] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17]
--operation mode is clrb_cntr

J3_q[17]_lut_out = (J3_q[17] $ (A1L04 & J3L53)) & A1L93;
J3_q[17] = DFFEA(J3_q[17]_lut_out, F1L93, , , A1L04, , );

--J3L73 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[17]~COUT
--operation mode is clrb_cntr

J3L73 = CARRY(J3_q[17] & J3L53);


--G1L5 is sum_control:inst5|out_control~239
--operation mode is normal

G1L5 = !J3_q[17] # !J3_q[10] # !J3_q[22] # !J3_q[6];


--J3_q[7] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]
--operation mode is clrb_cntr

J3_q[7]_lut_out = (J3_q[7] $ (A1L04 & J3L51)) & A1L93;
J3_q[7] = DFFEA(J3_q[7]_lut_out, F1L93, , , A1L04, , );

--J3L71 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT
--operation mode is clrb_cntr

J3L71 = CARRY(J3_q[7] & J3L51);


--J3_q[2] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr

J3_q[2]_lut_out = (J3_q[2] $ (A1L04 & J3L5)) & A1L93;
J3_q[2] = DFFEA(J3_q[2]_lut_out, F1L93, , , A1L04, , );

--J3L7 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is clrb_cntr

J3L7 = CARRY(J3_q[2] & J3L5);


--J3_q[0] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

J3_q[0]_lut_out = (A1L04 $ J3_q[0]) & A1L93;
J3_q[0] = DFFEA(J3_q[0]_lut_out, F1L93, , , A1L04, , );

--J3L3 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

J3L3 = CARRY(J3_q[0]);


--J3_q[4] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]
--operation mode is clrb_cntr

J3_q[4]_lut_out = (J3_q[4] $ (A1L04 & J3L9)) & A1L93;
J3_q[4] = DFFEA(J3_q[4]_lut_out, F1L93, , , A1L04, , );

--J3L11 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT
--operation mode is clrb_cntr

J3L11 = CARRY(J3_q[4] & J3L9);


--G1L6 is sum_control:inst5|out_control~240
--operation mode is normal

G1L6 = !J3_q[4] # !J3_q[0] # !J3_q[2] # !J3_q[7];


--G1L7 is sum_control:inst5|out_control~241
--operation mode is normal

G1L7 = G1L3 # G1L4 # G1L5 # G1L6;


--J3_q[15] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15]
--operation mode is clrb_cntr

J3_q[15]_lut_out = (J3_q[15] $ (A1L04 & J3L13)) & A1L93;
J3_q[15] = DFFEA(J3_q[15]_lut_out, F1L93, , , A1L04, , );

--J3L33 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[15]~COUT
--operation mode is clrb_cntr

J3L33 = CARRY(J3_q[15] & J3L13);


--J3_q[13] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13]
--operation mode is clrb_cntr

J3_q[13]_lut_out = (J3_q[13] $ (A1L04 & J3L72)) & A1L93;
J3_q[13] = DFFEA(J3_q[13]_lut_out, F1L93, , , A1L04, , );

--J3L92 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[13]~COUT
--operation mode is clrb_cntr

J3L92 = CARRY(J3_q[13] & J3L72);


--J3_q[21] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21]
--operation mode is clrb_cntr

J3_q[21]_lut_out = (J3_q[21] $ (A1L04 & J3L34)) & A1L93;
J3_q[21] = DFFEA(J3_q[21]_lut_out, F1L93, , , A1L04, , );

--J3L54 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[21]~COUT
--operation mode is clrb_cntr

J3L54 = CARRY(J3_q[21] & J3L34);


--J3_q[20] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20]
--operation mode is clrb_cntr

J3_q[20]_lut_out = (J3_q[20] $ (A1L04 & J3L14)) & A1L93;
J3_q[20] = DFFEA(J3_q[20]_lut_out, F1L93, , , A1L04, , );

--J3L34 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[20]~COUT
--operation mode is clrb_cntr

J3L34 = CARRY(J3_q[20] & J3L14);


--G1L8 is sum_control:inst5|out_control~242
--operation mode is normal

G1L8 = !J3_q[20] # !J3_q[21] # !J3_q[13] # !J3_q[15];


--J3_q[18] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18]
--operation mode is clrb_cntr

J3_q[18]_lut_out = (J3_q[18] $ (A1L04 & J3L73)) & A1L93;
J3_q[18] = DFFEA(J3_q[18]_lut_out, F1L93, , , A1L04, , );

--J3L93 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[18]~COUT
--operation mode is clrb_cntr

J3L93 = CARRY(J3_q[18] & J3L73);


--J3_q[5] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]
--operation mode is clrb_cntr

J3_q[5]_lut_out = (J3_q[5] $ (A1L04 & J3L11)) & A1L93;
J3_q[5] = DFFEA(J3_q[5]_lut_out, F1L93, , , A1L04, , );

--J3L31 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT
--operation mode is clrb_cntr

J3L31 = CARRY(J3_q[5] & J3L11);


--J3_q[19] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19]
--operation mode is clrb_cntr

J3_q[19]_lut_out = (J3_q[19] $ (A1L04 & J3L93)) & A1L93;
J3_q[19] = DFFEA(J3_q[19]_lut_out, F1L93, , , A1L04, , );

--J3L14 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[19]~COUT
--operation mode is clrb_cntr

J3L14 = CARRY(J3_q[19] & J3L93);


--J3_q[23] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23]
--operation mode is clrb_cntr

J3_q[23]_lut_out = (J3_q[23] $ (A1L04 & J3L74)) & A1L93;
J3_q[23] = DFFEA(J3_q[23]_lut_out, F1L93, , , A1L04, , );


--G1L9 is sum_control:inst5|out_control~243
--operation mode is normal

G1L9 = !J3_q[23] # !J3_q[19] # !J3_q[5] # !J3_q[18];


--J3_q[3] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is clrb_cntr

J3_q[3]_lut_out = (J3_q[3] $ (A1L04 & J3L7)) & A1L93;
J3_q[3] = DFFEA(J3_q[3]_lut_out, F1L93, , , A1L04, , );

--J3L9 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT
--operation mode is clrb_cntr

J3L9 = CARRY(J3_q[3] & J3L7);


--G1L2 is sum_control:inst5|out_control~4
--operation mode is normal

G1L2 = G1L7 # G1L8 # G1L9 # !J3_q[3];


--G1L11 is sum_control:inst5|reduce_nor~267
--operation mode is normal

G1L11 = !G1L12 # !G1L02 # !G1L91 # !G1L81;


--G1L01 is sum_control:inst5|out_control~246
--operation mode is normal

G1L01 = (!Reset & G1L11 # !G1L32 # !G1L22) & CASCADE(G1L2);


--J1_q[19] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[19]
--operation mode is clrb_cntr

J1_q[19]_lut_out = (J1_q[19] $ J1L93) & B1L1;
J1_q[19] = DFFEA(J1_q[19]_lut_out, Clock_8MHz, , , , , );

--J1L14 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[19]~COUT
--operation mode is clrb_cntr

J1L14 = CARRY(J1_q[19] & J1L93);


--E1_second_pulse_out[10] is second_pulse_latch:inst3|second_pulse_out[10]
--operation mode is normal

E1_second_pulse_out[10]_lut_out = !Reset & Acceleration[16] & !N3_cs_buffer[11] # !Acceleration[16] & N6_cs_buffer[10];
E1_second_pulse_out[10] = DFFEA(E1_second_pulse_out[10]_lut_out, J1_q[3], , , , , );


--F1L72 is pulse_sum:inst4|pulse_1~21
--operation mode is normal

F1L72 = F1L23 & E1_second_pulse_out[10] & J2_q[5] & !J2_q[4];


--F1_pulse_1[10] is pulse_sum:inst4|pulse_1[10]
--operation mode is normal

F1_pulse_1[10] = Reset & F1_pulse_1[10] # !Reset & F1L72;


--E1_second_pulse_out[9] is second_pulse_latch:inst3|second_pulse_out[9]
--operation mode is normal

E1_second_pulse_out[9]_lut_out = !Reset & Acceleration[16] & !N3_cs_buffer[10] # !Acceleration[16] & N6_cs_buffer[9];
E1_second_pulse_out[9] = DFFEA(E1_second_pulse_out[9]_lut_out, J1_q[3], , , , , );


--F1L62 is pulse_sum:inst4|pulse_1~19
--operation mode is normal

F1L62 = F1L33 & E1_second_pulse_out[9] & J2_q[6];


--F1_pulse_1[9] is pulse_sum:inst4|pulse_1[9]
--operation mode is normal

F1_pulse_1[9] = Reset & F1_pulse_1[9] # !Reset & F1L62;


--E1_second_pulse_out[8] is second_pulse_latch:inst3|second_pulse_out[8]
--operation mode is normal

E1_second_pulse_out[8]_lut_out = !Reset & Acceleration[16] & !N3_cs_buffer[9] # !Acceleration[16] & N6_cs_buffer[8];
E1_second_pulse_out[8] = DFFEA(E1_second_pulse_out[8]_lut_out, J1_q[3], , , , , );


--F1L52 is pulse_sum:inst4|pulse_1~17
--operation mode is normal

F1L52 = F1L33 & E1_second_pulse_out[8] & J2_q[7] & !J2_q[6];


--F1_pulse_1[8] is pulse_sum:inst4|pulse_1[8]
--operation mode is normal

F1_pulse_1[8] = Reset & F1_pulse_1[8] # !Reset & F1L52;


--E1_second_pulse_out[7] is second_pulse_latch:inst3|second_pulse_out[7]
--operation mode is normal

E1_second_pulse_out[7]_lut_out = !Reset & Acceleration[16] & !N3_cs_buffer[8] # !Acceleration[16] & N6_cs_buffer[7];
E1_second_pulse_out[7] = DFFEA(E1_second_pulse_out[7]_lut_out, J1_q[3], , , , , );


--F1L42 is pulse_sum:inst4|pulse_1~15
--operation mode is normal

F1L42 = F1L43 & E1_second_pulse_out[7] & J2_q[8];


--F1_pulse_1[7] is pulse_sum:inst4|pulse_1[7]
--operation mode is normal

F1_pulse_1[7] = Reset & F1_pulse_1[7] # !Reset & F1L42;


--E1_second_pulse_out[14] is second_pulse_latch:inst3|second_pulse_out[14]
--operation mode is normal

E1_second_pulse_out[14]_lut_out = !Reset & Acceleration[16] & !L1_unreg_res_node[15] # !Acceleration[16] & L2_unreg_res_node[14];
E1_second_pulse_out[14] = DFFEA(E1_second_pulse_out[14]_lut_out, J1_q[3], , , , , );


--F1L83 is pulse_sum:inst4|pulse_1~425
--operation mode is normal

F1L83 = J1_q[1] & E1_second_pulse_out[14] & J2_q[1] & !J2_q[0];


--F1_pulse_1[14] is pulse_sum:inst4|pulse_1[14]
--operation mode is normal

F1_pulse_1[14] = Reset & F1_pulse_1[14] # !Reset & F1L83;


--E1_second_pulse_out[13] is second_pulse_latch:inst3|second_pulse_out[13]
--operation mode is normal

E1_second_pulse_out[13]_lut_out = !Reset & Acceleration[16] & !N3_cs_buffer[14] # !Acceleration[16] & N6_cs_buffer[13];
E1_second_pulse_out[13] = DFFEA(E1_second_pulse_out[13]_lut_out, J1_q[3], , , , , );