main.tan.qmsg

一些很好的FPGA设计实例

{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "gate_control:inst3\|dp_s10hz~33 " "Info: Node \"gate_control:inst3\|dp_s10hz~33\"" {  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 12 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 12 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "gate_control:inst3\|dp_s1hz~33 " "Info: Node \"gate_control:inst3\|dp_s1hz~33\"" {  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 12 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 12 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Clock " "Info: Assuming node \"Clock\" is an undefined clock" {  } { { "main.bdf" "" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/main.bdf" { { 352 -224 -56 368 "Clock" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Clock" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "SW1 " "Info: Assuming node \"SW1\" is an undefined clock" {  } { { "main.bdf" "" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/main.bdf" { { 248 -224 -56 264 "SW1" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SW1" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "SW2 " "Info: Assuming node \"SW2\" is an undefined clock" {  } { { "main.bdf" "" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/main.bdf" { { 264 -224 -56 280 "SW2" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SW2" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "SW0 " "Info: Assuming node \"SW0\" is an undefined clock" {  } { { "main.bdf" "" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/main.bdf" { { 232 -224 -56 248 "SW0" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SW0" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "F_in " "Info: Assuming node \"F_in\" is an undefined clock" {  } { { "main.bdf" "" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/main.bdf" { { 56 -224 -56 72 "F_in" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "F_in" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "9 " "Warning: Found 9 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "gate_control:inst3\|wire_2 " "Info: Detected ripple clock \"gate_control:inst3\|wire_2\" as buffer" {  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 21 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "gate_control:inst3\|wire_2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "gate_control:inst3\|wire_1 " "Info: Detected ripple clock \"gate_control:inst3\|wire_1\" as buffer" {  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 58 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "gate_control:inst3\|wire_1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "gate_control:inst3\|fref~126 " "Info: Detected gated clock \"gate_control:inst3\|fref~126\" as buffer" {  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 19 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "gate_control:inst3\|fref~126" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "gate_control:inst3\|fref~114 " "Info: Detected gated clock \"gate_control:inst3\|fref~114\" as buffer" {  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 19 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "gate_control:inst3\|fref~114" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fdiv:inst1\|f1hz " "Info: Detected ripple clock \"fdiv:inst1\|f1hz\" as buffer" {  } { { "fdiv.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/fdiv.v" 3 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fdiv:inst1\|f1hz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fdiv:inst1\|f10hz " "Info: Detected ripple clock \"fdiv:inst1\|f10hz\" as buffer" {  } { { "fdiv.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/fdiv.v" 3 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fdiv:inst1\|f10hz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fdiv:inst1\|f100hz " "Info: Detected ripple clock \"fdiv:inst1\|f100hz\" as buffer" {  } { { "fdiv.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/fdiv.v" 3 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fdiv:inst1\|f100hz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fdiv:inst1\|f1khz " "Info: Detected ripple clock \"fdiv:inst1\|f1khz\" as buffer" {  } { { "fdiv.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/fdiv.v" 3 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fdiv:inst1\|f1khz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "gate_control:inst3\|always0~33sexpand1 " "Info: Detected gated clock \"gate_control:inst3\|always0~33sexpand1\" as buffer" {  } { { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "gate_control:inst3\|always0~33sexpand1" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clock register gate_control:inst3\|wire_1 register gate_control:inst3\|wire_2 22.42 MHz 44.6 ns Internal " "Info: Clock \"Clock\" has Internal fmax of 22.42 MHz between source register \"gate_control:inst3\|wire_1\" and destination register \"gate_control:inst3\|wire_2\" (period= 44.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.900 ns + Longest register register " "Info: + Longest register to register delay is 5.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns gate_control:inst3\|wire_1 1 REG LC209 114 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC209; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gate_control:inst3|wire_1 } "NODE_NAME" } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(2.600 ns) 5.900 ns gate_control:inst3\|wire_2 2 REG LC211 24 " "Info: 2: + IC(3.300 ns) + CELL(2.600 ns) = 5.900 ns; Loc. = LC211; Fanout = 24; REG Node = 'gate_control:inst3\|wire_2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.900 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns ( 44.07 % ) " "Info: Total cell delay = 2.600 ns ( 44.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns ( 55.93 % ) " "Info: Total interconnect delay = 3.300 ns ( 55.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.900 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.900 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } { 0.000ns 3.300ns } { 0.000ns 2.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-14.200 ns - Smallest " "Info: - Smallest clock skew is -14.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock destination 30.900 ns + Shortest register " "Info: + Shortest clock path from clock \"Clock\" to destination register is 30.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns Clock 1 CLK PIN_181 33 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_181; Fanout = 33; CLK Node = 'Clock'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Clock } "NODE_NAME" } } { "main.bdf" "" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/main.bdf" { { 352 -224 -56 368 "Clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 4.200 ns fdiv:inst1\|f1khz 2 REG LC225 42 " "Info: 2: + IC(0.000 ns) + CELL(1.400 ns) = 4.200 ns; Loc. = LC225; Fanout = 42; REG Node = 'fdiv:inst1\|f1khz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.400 ns" { Clock fdiv:inst1|f1khz } "NODE_NAME" } } { "fdiv.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/fdiv.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(4.000 ns) 11.400 ns fdiv:inst1\|f100hz 3 REG LC113 34 " "Info: 3: + IC(3.200 ns) + CELL(4.000 ns) = 11.400 ns; Loc. = LC113; Fanout = 34; REG Node = 'fdiv:inst1\|f100hz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.200 ns" { fdiv:inst1|f1khz fdiv:inst1|f100hz } "NODE_NAME" } } { "fdiv.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/fdiv.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(3.700 ns) 18.300 ns gate_control:inst3\|fref~114 4 COMB LC208 3 " "Info: 4: + IC(3.200 ns) + CELL(3.700 ns) = 18.300 ns; Loc. = LC208; Fanout = 3; COMB Node = 'gate_control:inst3\|fref~114'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.900 ns" { fdiv:inst1|f100hz gate_control:inst3|fref~114 } "NODE_NAME" } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.700 ns) 25.000 ns gate_control:inst3\|fref~126 5 COMB LOOP LC218 4 " "Info: 5: + IC(0.000 ns) + CELL(6.700 ns) = 25.000 ns; Loc. = LC218; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~126'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~126 LC218 " "Info: Loc. = LC218; Node \"gate_control:inst3\|fref~126\"" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 19 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.700 ns" { gate_control:inst3|fref~114 gate_control:inst3|fref~126 } "NODE_NAME" } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.900 ns) 30.900 ns gate_control:inst3\|wire_2 6 REG LC211 24 " "Info: 6: + IC(3.000 ns) + CELL(2.900 ns) = 30.900 ns; Loc. = LC211; Fanout = 24; REG Node = 'gate_control:inst3\|wire_2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.900 ns" { gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "21.500 ns ( 69.58 % ) " "Info: Total cell delay = 21.500 ns ( 69.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.400 ns ( 30.42 % ) " "Info: Total interconnect delay = 9.400 ns ( 30.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "30.900 ns" { Clock fdiv:inst1|f1khz fdiv:inst1|f100hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "30.900 ns" { Clock Clock~out fdiv:inst1|f1khz fdiv:inst1|f100hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } { 0.000ns 0.000ns 0.000ns 3.200ns 3.200ns 0.000ns 3.000ns } { 0.000ns 2.800ns 1.400ns 4.000ns 3.700ns 6.700ns 2.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock source 45.100 ns - Longest register " "Info: - Longest clock path from clock \"Clock\" to source register is 45.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns Clock 1 CLK PIN_181 33 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_181; Fanout = 33; CLK Node = 'Clock'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Clock } "NODE_NAME" } } { "main.bdf" "" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/main.bdf" { { 352 -224 -56 368 "Clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 4.200 ns fdiv:inst1\|f1khz 2 REG LC225 42 " "Info: 2: + IC(0.000 ns) + CELL(1.400 ns) = 4.200 ns; Loc. = LC225; Fanout = 42; REG Node = 'fdiv:inst1\|f1khz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.400 ns" { Clock fdiv:inst1|f1khz } "NODE_NAME" } } { "fdiv.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/fdiv.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(4.000 ns) 11.400 ns fdiv:inst1\|f100hz 3 REG LC113 34 " "Info: 3: + IC(3.200 ns) + CELL(4.000 ns) = 11.400 ns; Loc. = LC113; Fanout = 34; REG Node = 'fdiv:inst1\|f100hz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.200 ns" { fdiv:inst1|f1khz fdiv:inst1|f100hz } "NODE_NAME" } } { "fdiv.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/fdiv.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(4.000 ns) 18.600 ns fdiv:inst1\|f10hz 4 REG LC137 34 " "Info: 4: + IC(3.200 ns) + CELL(4.000 ns) = 18.600 ns; Loc. = LC137; Fanout = 34; REG Node = 'fdiv:inst1\|f10hz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.200 ns" { fdiv:inst1|f100hz fdiv:inst1|f10hz } "NODE_NAME" } } { "fdiv.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/fdiv.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(4.000 ns) 25.800 ns fdiv:inst1\|f1hz 5 REG LC153 1 " "Info: 5: + IC(3.200 ns) + CELL(4.000 ns) = 25.800 ns; Loc. = LC153; Fanout = 1; REG Node = 'fdiv:inst1\|f1hz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.200 ns" { fdiv:inst1|f10hz fdiv:inst1|f1hz } "NODE_NAME" } } { "fdiv.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/fdiv.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(3.700 ns) 32.500 ns gate_control:inst3\|fref~114 6 COMB LC208 3 " "Info: 6: + IC(3.000 ns) + CELL(3.700 ns) = 32.500 ns; Loc. = LC208; Fanout = 3; COMB Node = 'gate_control:inst3\|fref~114'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.700 ns" { fdiv:inst1|f1hz gate_control:inst3|fref~114 } "NODE_NAME" } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.700 ns) 39.200 ns gate_control:inst3\|fref~126 7 COMB LOOP LC218 4 " "Info: 7: + IC(0.000 ns) + CELL(6.700 ns) = 39.200 ns; Loc. = LC218; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~126'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~126 LC218 " "Info: Loc. = LC218; Node \"gate_control:inst3\|fref~126\"" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 19 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.700 ns" { gate_control:inst3|fref~114 gate_control:inst3|fref~126 } "NODE_NAME" } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.900 ns) 45.100 ns gate_control:inst3\|wire_1 8 REG LC209 114 " "Info: 8: + IC(3.000 ns) + CELL(2.900 ns) = 45.100 ns; Loc. = LC209; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.900 ns" { gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "29.500 ns ( 65.41 % ) " "Info: Total cell delay = 29.500 ns ( 65.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "15.600 ns ( 34.59 % ) " "Info: Total interconnect delay = 15.600 ns ( 34.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "45.100 ns" { Clock fdiv:inst1|f1khz fdiv:inst1|f100hz fdiv:inst1|f10hz fdiv:inst1|f1hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "45.100 ns" { Clock Clock~out fdiv:inst1|f1khz fdiv:inst1|f100hz fdiv:inst1|f10hz fdiv:inst1|f1hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.000ns 0.000ns 0.000ns 3.200ns 3.200ns 3.200ns 3.000ns 0.000ns 3.000ns } { 0.000ns 2.800ns 1.400ns 4.000ns 4.000ns 4.000ns 3.700ns 6.700ns 2.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "30.900 ns" { Clock fdiv:inst1|f1khz fdiv:inst1|f100hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "30.900 ns" { Clock Clock~out fdiv:inst1|f1khz fdiv:inst1|f100hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } { 0.000ns 0.000ns 0.000ns 3.200ns 3.200ns 0.000ns 3.000ns } { 0.000ns 2.800ns 1.400ns 4.000ns 3.700ns 6.700ns 2.900ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "45.100 ns" { Clock fdiv:inst1|f1khz fdiv:inst1|f100hz fdiv:inst1|f10hz fdiv:inst1|f1hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "45.100 ns" { Clock Clock~out fdiv:inst1|f1khz fdiv:inst1|f100hz fdiv:inst1|f10hz fdiv:inst1|f1hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.000ns 0.000ns 0.000ns 3.200ns 3.200ns 3.200ns 3.000ns 0.000ns 3.000ns } { 0.000ns 2.800ns 1.400ns 4.000ns 4.000ns 4.000ns 3.700ns 6.700ns 2.900ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 58 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.100 ns + " "Info: + Micro setup delay of destination is 1.100 ns" {  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 58 -1 0 } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 21 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.900 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.900 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } { 0.000ns 3.300ns } { 0.000ns 2.600ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "30.900 ns" { Clock fdiv:inst1|f1khz fdiv:inst1|f100hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "30.900 ns" { Clock Clock~out fdiv:inst1|f1khz fdiv:inst1|f100hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } { 0.000ns 0.000ns 0.000ns 3.200ns 3.200ns 0.000ns 3.000ns } { 0.000ns 2.800ns 1.400ns 4.000ns 3.700ns 6.700ns 2.900ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "45.100 ns" { Clock fdiv:inst1|f1khz fdiv:inst1|f100hz fdiv:inst1|f10hz fdiv:inst1|f1hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "45.100 ns" { Clock Clock~out fdiv:inst1|f1khz fdiv:inst1|f100hz fdiv:inst1|f10hz fdiv:inst1|f1hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.000ns 0.000ns 0.000ns 3.200ns 3.200ns 3.200ns 3.000ns 0.000ns 3.000ns } { 0.000ns 2.800ns 1.400ns 4.000ns 4.000ns 4.000ns 3.700ns 6.700ns 2.900ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}