main.tan.qmsg

来自「一些很好的FPGA设计实例」· QMSG 代码 · 共 22 行 · 第 1/5 页

{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dispdecoder:inst5\|data_out\[0\]~150 " "Info: Node \"dispdecoder:inst5\|data_out\[0\]~150\"" {  } { { "dispdecoder.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/dispdecoder.v" 31 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "dispdecoder.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/dispdecoder.v" 31 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dispdecoder:inst5\|data_out\[4\]~146 " "Info: Node \"dispdecoder:inst5\|data_out\[4\]~146\"" {  } { { "dispdecoder.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/dispdecoder.v" 31 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "dispdecoder.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/dispdecoder.v" 31 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dispdecoder:inst5\|data_out\[5\]~142 " "Info: Node \"dispdecoder:inst5\|data_out\[5\]~142\"" {  } { { "dispdecoder.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/dispdecoder.v" 31 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "dispdecoder.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/dispdecoder.v" 31 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "gate_control:inst3\|fref~126 " "Info: Node \"gate_control:inst3\|fref~126\"" {  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 19 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 19 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "gate_control:inst3\|dp_s100hz~33 " "Info: Node \"gate_control:inst3\|dp_s100hz~33\"" {  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 12 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 12 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}