main.tan.qmsg

一些很好的FPGA设计实例

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dispdecoder:inst5\|data_out\[2\]~166 " "Info: Node \"dispdecoder:inst5\|data_out\[2\]~166\"" {  } { { "dispdecoder.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/dispdecoder.v" 31 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "dispdecoder.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/dispdecoder.v" 31 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dispdecoder:inst5\|data_out\[3\]~162 " "Info: Node \"dispdecoder:inst5\|data_out\[3\]~162\"" {  } { { "dispdecoder.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/dispdecoder.v" 31 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "dispdecoder.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/dispdecoder.v" 31 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dispdecoder:inst5\|data_out\[1\]~158 " "Info: Node \"dispdecoder:inst5\|data_out\[1\]~158\"" {  } { { "dispdecoder.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/dispdecoder.v" 31 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "dispdecoder.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/dispdecoder.v" 31 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dispdecoder:inst5\|data_out\[6\]~154 " "Info: Node \"dispdecoder:inst5\|data_out\[6\]~154\"" {  } { { "dispdecoder.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/dispdecoder.v" 31 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "dispdecoder.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/dispdecoder.v" 31 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}