main.map.qmsg

一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 23 09:50:45 2008 " "Info: Processing started: Fri May 23 09:50:45 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off main -c main " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off main -c main" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "main.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file main.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 main " "Info: Found entity 1: main" {  } { { "main.bdf" "" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/main.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file counter.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter " "Info: Found entity 1: counter" {  } { { "counter.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/counter.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_mux.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file data_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_mux " "Info: Found entity 1: data_mux" {  } { { "data_mux.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/data_mux.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dispdecoder.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dispdecoder.v" { { "Info" "ISGN_ENTITY_NAME" "1 dispdecoder " "Info: Found entity 1: dispdecoder" {  } { { "dispdecoder.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/dispdecoder.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dispselect.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dispselect.v" { { "Info" "ISGN_ENTITY_NAME" "1 dispselect " "Info: Found entity 1: dispselect" {  } { { "dispselect.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/dispselect.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "fdiv.v(9) " "Warning (10268): Verilog HDL information at fdiv.v(9): Always Construct contains both blocking and non-blocking assignments" {  } { { "fdiv.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/fdiv.v" 9 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "fdiv.v(24) " "Warning (10268): Verilog HDL information at fdiv.v(24): Always Construct contains both blocking and non-blocking assignments" {  } { { "fdiv.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/fdiv.v" 24 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "fdiv.v(39) " "Warning (10268): Verilog HDL information at fdiv.v(39): Always Construct contains both blocking and non-blocking assignments" {  } { { "fdiv.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/fdiv.v" 39 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "fdiv.v(54) " "Warning (10268): Verilog HDL information at fdiv.v(54): Always Construct contains both blocking and non-blocking assignments" {  } { { "fdiv.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/fdiv.v" 54 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fdiv.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fdiv.v" { { "Info" "ISGN_ENTITY_NAME" "1 fdiv " "Info: Found entity 1: fdiv" {  } { { "fdiv.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/fdiv.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "flip_latch.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file flip_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 flip_latch " "Info: Found entity 1: flip_latch" {  } { { "flip_latch.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/flip_latch.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gate_control.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file gate_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 gate_control " "Info: Found entity 1: gate_control" {  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "main " "Info: Elaborating entity \"main\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:inst " "Info: Elaborating entity \"counter\" for hierarchy \"counter:inst\"" {  } { { "main.bdf" "inst" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/main.bdf" { { 0 136 256 160 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_IGNORE_INIT" "counter.v(15) " "Warning (10101): Verilog HDL unsupported feature warning at counter.v(15): Initial Construct is not supported and will be ignored" {  } { { "counter.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/counter.v" 15 0 0 } }  } 0 10101 "Verilog HDL unsupported feature warning at %1!s!: Initial Construct is not supported and will be ignored" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "gate_control gate_control:inst3 " "Info: Elaborating entity \"gate_control\" for hierarchy \"gate_control:inst3\"" {  } { { "main.bdf" "inst3" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/main.bdf" { { 208 80 224 368 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_IGNORE_INIT" "gate_control.v(25) " "Warning (10101): Verilog HDL unsupported feature warning at gate_control.v(25): Initial Construct is not supported and will be ignored" {  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 25 0 0 } }  } 0 10101 "Verilog HDL unsupported feature warning at %1!s!: Initial Construct is not supported and will be ignored" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "fref gate_control.v(34) " "Warning (10240): Verilog HDL Always Construct warning at gate_control.v(34): inferring latch(es) for variable \"fref\", which holds its previous value in one or more paths through the always construct" {  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 34 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "fref gate_control.v(36) " "Info (10041): Verilog HDL or VHDL info at gate_control.v(36): inferred latch for \"fref\"" {  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "dp_s1hz gate_control.v(34) " "Warning (10240): Verilog HDL Always Construct warning at gate_control.v(34): inferring latch(es) for variable \"dp_s1hz\", which holds its previous value in one or more paths through the always construct" {  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 34 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "dp_s1hz gate_control.v(12) " "Info (10041): Verilog HDL or VHDL info at gate_control.v(12): inferred latch for \"dp_s1hz\"" {  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 12 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "dp_s10hz gate_control.v(34) " "Warning (10240): Verilog HDL Always Construct warning at gate_control.v(34): inferring latch(es) for variable \"dp_s10hz\", which holds its previous value in one or more paths through the always construct" {  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 34 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "dp_s10hz gate_control.v(12) " "Info (10041): Verilog HDL or VHDL info at gate_control.v(12): inferred latch for \"dp_s10hz\"" {  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 12 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "dp_s100hz gate_control.v(34) " "Warning (10240): Verilog HDL Always Construct warning at gate_control.v(34): inferring latch(es) for variable \"dp_s100hz\", which holds its previous value in one or more paths through the always construct" {  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 34 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}