main.fit.rpt

一些很好的FPGA设计实例

Fitter report for main
Fri May 23 09:51:22 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Pin-Out File
  5. Fitter Resource Usage Summary
  6. Input Pins
  7. Output Pins
  8. All Package Pins
  9. I/O Standard
 10. Dedicated Inputs I/O
 11. Output Pin Default Load For Reported TCO
 12. Fitter Resource Utilization by Entity
 13. Control Signals
 14. Global & Other Fast Signals
 15. Non-Global High Fan-Out Signals
 16. Interconnect Usage Summary
 17. LAB External Interconnect
 18. LAB Macrocells
 19. Parallel Expander
 20. Shareable Expander
 21. Logic Cell Interconnection
 22. Fitter Device Options
 23. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------+
; Fitter Summary                                                   ;
+-----------------------+------------------------------------------+
; Fitter Status         ; Successful - Fri May 23 09:51:22 2008    ;
; Quartus II Version    ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name         ; main                                     ;
; Top-level Entity Name ; main                                     ;
; Family                ; MAX7000S                                 ;
; Device                ; EPM7256SQC208-7                          ;
; Timing Models         ; Final                                    ;
; Total macrocells      ; 250 / 256 ( 98 % )                       ;
; Total pins            ; 24 / 164 ( 15 % )                        ;
+-----------------------+------------------------------------------+


+-----------------------------------------------------------------------+
; Fitter Settings                                                       ;
+--------------------------------------------+----------+---------------+
; Option                                     ; Setting  ; Default Value ;
+--------------------------------------------+----------+---------------+
; Device                                     ; AUTO     ;               ;
; Use smart compilation                      ; Off      ; Off           ;
; Optimize IOC Register Placement for Timing ; On       ; On            ;
; Limit to One Fitting Attempt               ; Off      ; Off           ;
; Fitter Initial Placement Seed              ; 1        ; 1             ;
; Slow Slew Rate                             ; Off      ; Off           ;
; Fitter Effort                              ; Auto Fit ; Auto Fit      ;
+--------------------------------------------+----------+---------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/main.pin.


+---------------------------------------------------------------+
; Fitter Resource Usage Summary                                 ;
+-----------------------------------+---------------------------+
; Resource                          ; Usage                     ;
+-----------------------------------+---------------------------+
; Logic cells                       ; 250 / 256 ( 98 % )        ;
; Registers                         ; 192 / 256 ( 75 % )        ;
; Number of pterms used             ; 697                       ;
; User inserted logic elements      ; 0                         ;
; I/O pins                          ; 24 / 164 ( 15 % )         ;
;     -- Clock pins                 ; 2 / 2 ( 100 % )           ;
;     -- Dedicated input pins       ; 0 / 2 ( 0 % )             ;
; Global signals                    ; 2                         ;
; Shareable expanders               ; 30 / 256 ( 12 % )         ;
; Parallel expanders                ; 9 / 240 ( 4 % )           ;
; Cells using turbo bit             ; 250 / 256 ( 98 % )        ;
; Maximum fan-out node              ; gate_control:inst3|wire_1 ;
; Maximum fan-out                   ; 56                        ;
; Highest non-global fan-out signal ; gate_control:inst3|wire_1 ;
; Highest non-global fan-out        ; 56                        ;
; Total fan-out                     ; 3219                      ;
; Average fan-out                   ; 10.59                     ;
+-----------------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                  ;
+-------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+
; Name  ; Pin # ; I/O Bank ; LAB ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; I/O Standard ; Location assigned by ;
+-------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+
; Clock ; 181   ; --       ; --  ; 33                    ; 0                  ; yes    ; no             ; TTL          ; Fitter               ;
; F_in  ; 184   ; --       ; --  ; 25                    ; 0                  ; yes    ; no             ; TTL          ; Fitter               ;