main.map.rpt

来自「一些很好的FPGA设计实例」· RPT 代码 · 共 558 行 · 第 1/4 页

; IGNORE_CARRY_BUFFERS   ; OFF               ; IGNORE_CARRY                          ;
; AUTO_CASCADE_CHAINS    ; ON                ; AUTO_CASCADE                          ;
; IGNORE_CASCADE_BUFFERS ; OFF               ; IGNORE_CASCADE                        ;
; LPM_WIDTH              ; 32                ; Untyped                               ;
; LPM_DIRECTION          ; UP                ; Untyped                               ;
; LPM_MODULUS            ; 0                 ; Untyped                               ;
; LPM_AVALUE             ; UNUSED            ; Untyped                               ;
; LPM_SVALUE             ; UNUSED            ; Untyped                               ;
; LPM_PORT_UPDOWN        ; PORT_CONNECTIVITY ; Untyped                               ;
; DEVICE_FAMILY          ; MAX7000S          ; Untyped                               ;
; CARRY_CHAIN            ; MANUAL            ; Untyped                               ;
; CARRY_CHAIN_LENGTH     ; 48                ; CARRY_CHAIN_LENGTH                    ;
; NOT_GATE_PUSH_BACK     ; ON                ; NOT_GATE_PUSH_BACK                    ;
; CARRY_CNT_EN           ; SMART             ; Untyped                               ;
; LABWIDE_SCLR           ; ON                ; Untyped                               ;
; USE_NEW_VERSION        ; TRUE              ; Untyped                               ;
; CBXI_PARAMETER         ; NOTHING           ; Untyped                               ;
+------------------------+-------------------+---------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: fdiv:inst1|lpm_counter:cnt3_rtl_9 ;
+------------------------+-------------------+---------------------------------------+
; Parameter Name         ; Value             ; Type                                  ;
+------------------------+-------------------+---------------------------------------+
; AUTO_CARRY_CHAINS      ; ON                ; AUTO_CARRY                            ;
; IGNORE_CARRY_BUFFERS   ; OFF               ; IGNORE_CARRY                          ;
; AUTO_CASCADE_CHAINS    ; ON                ; AUTO_CASCADE                          ;
; IGNORE_CASCADE_BUFFERS ; OFF               ; IGNORE_CASCADE                        ;
; LPM_WIDTH              ; 32                ; Untyped                               ;
; LPM_DIRECTION          ; UP                ; Untyped                               ;
; LPM_MODULUS            ; 0                 ; Untyped                               ;
; LPM_AVALUE             ; UNUSED            ; Untyped                               ;
; LPM_SVALUE             ; UNUSED            ; Untyped                               ;
; LPM_PORT_UPDOWN        ; PORT_CONNECTIVITY ; Untyped                               ;
; DEVICE_FAMILY          ; MAX7000S          ; Untyped                               ;
; CARRY_CHAIN            ; MANUAL            ; Untyped                               ;
; CARRY_CHAIN_LENGTH     ; 48                ; CARRY_CHAIN_LENGTH                    ;
; NOT_GATE_PUSH_BACK     ; ON                ; NOT_GATE_PUSH_BACK                    ;
; CARRY_CNT_EN           ; SMART             ; Untyped                               ;
; LABWIDE_SCLR           ; ON                ; Untyped                               ;
; USE_NEW_VERSION        ; TRUE              ; Untyped                               ;
; CBXI_PARAMETER         ; NOTHING           ; Untyped                               ;
+------------------------+-------------------+---------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Fri May 23 09:50:45 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off main -c main
Info: Found 1 design units, including 1 entities, in source file main.bdf
    Info: Found entity 1: main
Info: Found 1 design units, including 1 entities, in source file counter.v
    Info: Found entity 1: counter
Info: Found 1 design units, including 1 entities, in source file data_mux.v
    Info: Found entity 1: data_mux
Info: Found 1 design units, including 1 entities, in source file dispdecoder.v
    Info: Found entity 1: dispdecoder
Info: Found 1 design units, including 1 entities, in source file dispselect.v
    Info: Found entity 1: dispselect
Info: Found 1 design units, including 1 entities, in source file fdiv.v
    Info: Found entity 1: fdiv
Info: Found 1 design units, including 1 entities, in source file flip_latch.v
    Info: Found entity 1: flip_latch
Info: Found 1 design units, including 1 entities, in source file gate_control.v
    Info: Found entity 1: gate_control
Info: Elaborating entity "main" for the top level hierarchy
Info: Elaborating entity "counter" for hierarchy "counter:inst"
Warning (10101): Verilog HDL unsupported feature warning at counter.v(15): Initial Construct is not supported and will be ignored
Info: Elaborating entity "gate_control" for hierarchy "gate_control:inst3"
Warning (10101): Verilog HDL unsupported feature warning at gate_control.v(25): Initial Construct is not supported and will be ignored
Warning (10240): Verilog HDL Always Construct warning at gate_control.v(34): inferring latch(es) for variable "fref", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at gate_control.v(36): inferred latch for "fref"
Warning (10240): Verilog HDL Always Construct warning at gate_control.v(34): inferring latch(es) for variable "dp_s1hz", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at gate_control.v(12): inferred latch for "dp_s1hz"
Warning (10240): Verilog HDL Always Construct warning at gate_control.v(34): inferring latch(es) for variable "dp_s10hz", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at gate_control.v(12): inferred latch for "dp_s10hz"
Warning (10240): Verilog HDL Always Construct warning at gate_control.v(34): inferring latch(es) for variable "dp_s100hz", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at gate_control.v(12): inferred latch for "dp_s100hz"
Info: Elaborating entity "fdiv" for hierarchy "fdiv:inst1"
Info: Elaborating entity "dispdecoder" for hierarchy "dispdecoder:inst5"
Warning (10101): Verilog HDL unsupported feature warning at dispdecoder.v(24): Initial Construct is not supported and will be ignored
Warning (10240): Verilog HDL Always Construct warning at dispdecoder.v(29): inferring latch(es) for variable "data_out", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at dispdecoder.v(31): inferred latch for "data_out[6]"
Info (10041): Verilog HDL or VHDL info at dispdecoder.v(31): inferred latch for "data_out[5]"
Info (10041): Verilog HDL or VHDL info at dispdecoder.v(31): inferred latch for "data_out[4]"
Info (10041): Verilog HDL or VHDL info at dispdecoder.v(31): inferred latch for "data_out[3]"
Info (10041): Verilog HDL or VHDL info at dispdecoder.v(31): inferred latch for "data_out[2]"
Info (10041): Verilog HDL or VHDL info at dispdecoder.v(31): inferred latch for "data_out[1]"
Info (10041): Verilog HDL or VHDL info at dispdecoder.v(31): inferred latch for "data_out[0]"
Info: Elaborating entity "data_mux" for hierarchy "data_mux:inst8"
Info: Elaborating entity "flip_latch" for hierarchy "flip_latch:inst2"
Info: Elaborating entity "dispselect" for hierarchy "dispselect:inst7"
Info: Inferred 10 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "counter:inst|Q5[0]~176"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "counter:inst|Q0[0]~4"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "counter:inst|Q1[0]~128"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "counter:inst|Q2[0]~140"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "counter:inst|Q3[0]~152"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "counter:inst|Q4[0]~164"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: "fdiv:inst1|cnt1[0]~32"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: "fdiv:inst1|cnt2[0]~32"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: "fdiv:inst1|cnt4[0]~32"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: "fdiv:inst1|cnt3[0]~32"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Elaborated megafunction instantiation "counter:inst|lpm_counter:Q5_rtl_0"
Info: Elaborated megafunction instantiation "counter:inst|lpm_counter:Q0_rtl_1"
Info: Elaborated megafunction instantiation "fdiv:inst1|lpm_counter:cnt1_rtl_6"
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "Clock" to global clock signal
    Info: Promoted clock signal driven by pin "F_in" to global clock signal
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "Clock" to global clock signal
    Info: Promoted clock signal driven by pin "F_in" to global clock signal
Info: Implemented 299 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 15 output pins
    Info: Implemented 250 macrocells
    Info: Implemented 29 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings
    Info: Processing ended: Fri May 23 09:51:12 2008
    Info: Elapsed time: 00:00:28


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/main.map.smsg.