main.tan.summary

一些很好的FPGA设计实例

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 75.300 ns
From           : flip_latch:inst2|Q5[2]
To             : disp_data[5]
From Clock     : Clock
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 29.100 ns
From           : SW2
To             : disp_data[5]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'Clock'
Slack          : N/A
Required Time  : None
Actual Time    : 22.42 MHz ( period = 44.600 ns )
From           : gate_control:inst3|wire_1
To             : gate_control:inst3|wire_2
From Clock     : Clock
To Clock       : Clock
Failed Paths   : 0

Type           : Clock Setup: 'SW2'
Slack          : N/A
Required Time  : None
Actual Time    : 33.78 MHz ( period = 29.600 ns )
From           : gate_control:inst3|wire_1
To             : gate_control:inst3|wire_2
From Clock     : SW2
To Clock       : SW2
Failed Paths   : 0

Type           : Clock Setup: 'SW1'
Slack          : N/A
Required Time  : None
Actual Time    : 33.78 MHz ( period = 29.600 ns )
From           : gate_control:inst3|wire_1
To             : gate_control:inst3|wire_2
From Clock     : SW1
To Clock       : SW1
Failed Paths   : 0

Type           : Clock Setup: 'SW0'
Slack          : N/A
Required Time  : None
Actual Time    : 41.67 MHz ( period = 24.000 ns )
From           : gate_control:inst3|wire_1
To             : gate_control:inst3|wire_2
From Clock     : SW0
To Clock       : SW0
Failed Paths   : 0

Type           : Clock Setup: 'F_in'
Slack          : N/A
Required Time  : None
Actual Time    : 54.05 MHz ( period = 18.500 ns )
From           : counter:inst|lpm_counter:Q2_rtl_3|dffs[1]
To             : counter:inst|F_OUT
From Clock     : F_in
To Clock       : F_in
Failed Paths   : 0

Type           : Clock Hold: 'Clock'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : gate_control:inst3|wire_1
To             : gate_control:inst3|wire_1
From Clock     : Clock
To Clock       : Clock
Failed Paths   : 2

Type           : Clock Hold: 'SW1'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : gate_control:inst3|wire_1
To             : gate_control:inst3|wire_1
From Clock     : SW1
To Clock       : SW1
Failed Paths   : 2

Type           : Clock Hold: 'SW2'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : gate_control:inst3|wire_1
To             : gate_control:inst3|wire_1
From Clock     : SW2
To Clock       : SW2
Failed Paths   : 2

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 6

--------------------------------------------------------------------------------------