main.tan.rpt

一些很好的FPGA设计实例

; Clock Hold: 'SW1'            ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; gate_control:inst3|wire_1                 ; gate_control:inst3|wire_1 ; SW1        ; SW1      ; 2            ;
; Clock Hold: 'SW2'            ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; gate_control:inst3|wire_1                 ; gate_control:inst3|wire_1 ; SW2        ; SW2      ; 2            ;
; Total number of failed paths ;                                          ;               ;                                  ;                                           ;                           ;            ;          ; 6            ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-------------------------------------------+---------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM7256SQC208-7    ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; SW1             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; SW2             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; SW0             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; F_in            ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'Clock'                                                                                                                                                                                                                                                                                ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------+--------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                       ; To                                         ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------+--------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 22.42 MHz ( period = 44.600 ns )                    ; gate_control:inst3|wire_1                  ; gate_control:inst3|wire_2                  ; Clock      ; Clock    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; gate_control:inst3|wire_1                  ; gate_control:inst3|wire_1                  ; Clock      ; Clock    ; None                        ; None                      ; 5.600 ns                ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[3]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[2]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[3]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[2]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[3]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[2]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;