📄 cfq.tan.rpt
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Timing Analyzer report for cfq
Wed May 16 18:36:07 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. tsu
6. tco
7. th
8. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+--------+--------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+--------+--------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 1.100 ns ; data ; q~reg0 ; -- ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 10.800 ns ; q~reg0 ; q ; clk ; -- ; 0 ;
; Worst-case th ; N/A ; None ; 0.500 ns ; data ; q~reg0 ; -- ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+--------+--------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1K10QC208-2 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+------+--------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+------+--------+----------+
; N/A ; None ; 1.100 ns ; data ; q~reg0 ; clk ;
+-------+--------------+------------+------+--------+----------+
+--------------------------------------------------------------+
; tco ;
+-------+--------------+------------+--------+----+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+--------+----+------------+
; N/A ; None ; 10.800 ns ; q~reg0 ; q ; clk ;
+-------+--------------+------------+--------+----+------------+
+--------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+------+--------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+------+--------+----------+
; N/A ; None ; 0.500 ns ; data ; q~reg0 ; clk ;
+---------------+-------------+-----------+------+--------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Wed May 16 18:36:06 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cfq -c cfq
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: No valid register-to-register data paths exist for clock "clk"
Info: tsu for register "q~reg0" (data pin = "data", clock pin = "clk") is 1.100 ns
Info: + Longest pin to register delay is 5.200 ns
Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_47; Fanout = 1; PIN Node = 'data'
Info: 2: + IC(1.200 ns) + CELL(0.500 ns) = 5.200 ns; Loc. = LC8_C15; Fanout = 1; REG Node = 'q~reg0'
Info: Total cell delay = 4.000 ns ( 76.92 % )
Info: Total interconnect delay = 1.200 ns ( 23.08 % )
Info: + Micro setup delay of destination is 0.600 ns
Info: - Shortest clock path from clock "clk" to destination register is 4.700 ns
Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_46; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(1.200 ns) + CELL(0.000 ns) = 4.700 ns; Loc. = LC8_C15; Fanout = 1; REG Node = 'q~reg0'
Info: Total cell delay = 3.500 ns ( 74.47 % )
Info: Total interconnect delay = 1.200 ns ( 25.53 % )
Info: tco from clock "clk" to destination pin "q" through register "q~reg0" is 10.800 ns
Info: + Longest clock path from clock "clk" to source register is 4.700 ns
Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_46; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(1.200 ns) + CELL(0.000 ns) = 4.700 ns; Loc. = LC8_C15; Fanout = 1; REG Node = 'q~reg0'
Info: Total cell delay = 3.500 ns ( 74.47 % )
Info: Total interconnect delay = 1.200 ns ( 25.53 % )
Info: + Micro clock to output delay of source is 0.400 ns
Info: + Longest register to pin delay is 5.700 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_C15; Fanout = 1; REG Node = 'q~reg0'
Info: 2: + IC(1.100 ns) + CELL(4.600 ns) = 5.700 ns; Loc. = PIN_19; Fanout = 0; PIN Node = 'q'
Info: Total cell delay = 4.600 ns ( 80.70 % )
Info: Total interconnect delay = 1.100 ns ( 19.30 % )
Info: th for register "q~reg0" (data pin = "data", clock pin = "clk") is 0.500 ns
Info: + Longest clock path from clock "clk" to destination register is 4.700 ns
Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_46; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(1.200 ns) + CELL(0.000 ns) = 4.700 ns; Loc. = LC8_C15; Fanout = 1; REG Node = 'q~reg0'
Info: Total cell delay = 3.500 ns ( 74.47 % )
Info: Total interconnect delay = 1.200 ns ( 25.53 % )
Info: + Micro hold delay of destination is 1.000 ns
Info: - Shortest pin to register delay is 5.200 ns
Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_47; Fanout = 1; PIN Node = 'data'
Info: 2: + IC(1.200 ns) + CELL(0.500 ns) = 5.200 ns; Loc. = LC8_C15; Fanout = 1; REG Node = 'q~reg0'
Info: Total cell delay = 4.000 ns ( 76.92 % )
Info: Total interconnect delay = 1.200 ns ( 23.08 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Wed May 16 18:36:07 2007
Info: Elapsed time: 00:00:01
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