alu.map.qmsg

一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 20 21:29:20 2007 " "Info: Processing started: Tue Mar 20 21:29:20 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ALU -c ALU " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ALU -c ALU" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"USE\";  expecting \"(\", or \"'\", or \".\" ALU.vhd(3) " "Error (10500): VHDL syntax error at ALU.vhd(3) near text \"USE\";  expecting \"(\", or \"'\", or \".\"" {  } { { "ALU.vhd" "" { Text "E:/altera/ALU/ALU.vhd" 3 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"END\";  expecting an identifier (\"end\" is a reserved keyword), or \"constant\", or \"file\", or \"signal\", or \"variable\" ALU.vhd(12) " "Error (10500): VHDL syntax error at ALU.vhd(12) near text \"END\";  expecting an identifier (\"end\" is a reserved keyword), or \"constant\", or \"file\", or \"signal\", or \"variable\"" {  } { { "ALU.vhd" "" { Text "E:/altera/ALU/ALU.vhd" 12 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"BEGIN\";  expecting an identifier (\"begin\" is a reserved keyword), or \"constant\", or \"file\", or \"signal\", or \"variable\" ALU.vhd(17) " "Error (10500): VHDL syntax error at ALU.vhd(17) near text \"BEGIN\";  expecting an identifier (\"begin\" is a reserved keyword), or \"constant\", or \"file\", or \"signal\", or \"variable\"" {  } { { "ALU.vhd" "" { Text "E:/altera/ALU/ALU.vhd" 17 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\")\";  expecting \":\", or \",\" ALU.vhd(19) " "Error (10500): VHDL syntax error at ALU.vhd(19) near text \")\";  expecting \":\", or \",\"" {  } { { "ALU.vhd" "" { Text "E:/altera/ALU/ALU.vhd" 19 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ALU.vhd 0 0 " "Info: Found 0 design units, including 0 entities, in source file ALU.vhd" {  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"USE\";  expecting \"(\", or \"'\", or \".\" count60.vhd(3) " "Error (10500): VHDL syntax error at count60.vhd(3) near text \"USE\";  expecting \"(\", or \"'\", or \".\"" {  } { { "../shizhongjishuqi/count60.vhd" "" { Text "E:/altera/shizhongjishuqi/count60.vhd" 3 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"'\";  expecting \"(\", or an identifier, or  unary operator,  count60.vhd(8) " "Error (10500): VHDL syntax error at count60.vhd(8) near text \"'\";  expecting \"(\", or an identifier, or  unary operator, " {  } { { "../shizhongjishuqi/count60.vhd" "" { Text "E:/altera/shizhongjishuqi/count60.vhd" 8 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"END\";  expecting an identifier (\"end\" is a reserved keyword), or \"constant\", or \"file\", or \"signal\", or \"variable\" count60.vhd(10) " "Error (10500): VHDL syntax error at count60.vhd(10) near text \"END\";  expecting an identifier (\"end\" is a reserved keyword), or \"constant\", or \"file\", or \"signal\", or \"variable\"" {  } { { "../shizhongjishuqi/count60.vhd" "" { Text "E:/altera/shizhongjishuqi/count60.vhd" 10 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"BEGIN\";  expecting an identifier (\"begin\" is a reserved keyword), or \"constant\", or \"file\", or \"signal\", or \"variable\" count60.vhd(13) " "Error (10500): VHDL syntax error at count60.vhd(13) near text \"BEGIN\";  expecting an identifier (\"begin\" is a reserved keyword), or \"constant\", or \"file\", or \"signal\", or \"variable\"" {  } { { "../shizhongjishuqi/count60.vhd" "" { Text "E:/altera/shizhongjishuqi/count60.vhd" 13 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../shizhongjishuqi/count60.vhd 0 0 " "Info: Found 0 design units, including 0 entities, in source file ../shizhongjishuqi/count60.vhd" {  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 8 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 8 errors, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Tue Mar 20 21:29:22 2007 " "Error: Processing ended: Tue Mar 20 21:29:22 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}