alu.vhd

一些很好的FPGA设计实例

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ALU IS
PORT(
    S:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
    A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    F:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    M:IN STD_LOGIC;
    CO:OUT  STD_LOGIC; 
END ALU;
ARCHITECTURE behav OF ALU IS
 SIGNAL A9:  STD_LOGIC_VECTOR(8 DOWNTO 0);
 SIGNAL B9:  STD_LOGIC_VECTOR(8 DOWNTO 0);
 SIGNAL F9:  STD_LOGIC_VECTOR(8 DOWNTO 0);
 BEGIN 
        A9<='0'&A;B9<='0'B
PROCESS(M,CO,A9,B9)
 BEGIN
 CASE S IS
 WHEN "000"=>IF M='0' THEN F9<=NOT A9;
     ELSE F9<=NOT A9+1;
     END IF;
 WHEN "001"=>IF M='0' THEN F9<=NOT (A9 OR B9);
     ELSE F9<=A9+A9;
     END IF;
 WHEN "010"=>IF M='0' THEN F9<=A9;
     ELSE F9<=A9+B9;
     END IF;
 WHEN "011"=>IF M='0' THEN F9<="000000000";
     ELSE F9<=A9+B9+1;
     END IF;
 WHEN "100"=>IF M='0' THEN F9<=NOT(A9 AND B9);
     ELSE F9<=(A9-B9);
     END IF;
 WHEN "101"=>IF M='0' THEN F9<=NOT B9;
     ELSE F9<=A9-B9-1;
     END IF;
 WHEN "110"=>IF M='0' THEN F9<=A9 XOR B9;
     ELSE F9<=A9;
     END IF;
 WHEN "111"=>IF M='0' THEN F9<=NOT(A9 XOR B9);
     ELSE F9<=B9;
     END IF;
 WHEN OTHERS =>F9<="00000000";
 END CASE;
END PROCESS;
 F<=F9(7 DOWNTO 0);  CO<=F9;
END behav;