full_multi.tan.qmsg

一些很好的FPGA设计实例

{ "Info" "ITDB_TH_RESULT" "smdisplay:inst2\|74175:inst7\|15 a\[3\] CLK -4.500 ns register " "Info: th for register \"smdisplay:inst2\|74175:inst7\|15\" (data pin = \"a\[3\]\", clock pin = \"CLK\") is -4.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.800 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK 1 CLK PIN_79 19 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 19; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "full_multi.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/aaa/full_multi.bdf" { { 144 128 296 160 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.000 ns) 1.800 ns smdisplay:inst2\|74175:inst7\|15 2 REG LC2_F21 4 " "Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC2_F21; Fanout = 4; REG Node = 'smdisplay:inst2\|74175:inst7\|15'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { CLK smdisplay:inst2|74175:inst7|15 } "NODE_NAME" } } { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 184 352 416 264 "15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 83.33 % ) " "Info: Total cell delay = 1.500 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.300 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { CLK smdisplay:inst2|74175:inst7|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { CLK CLK~out smdisplay:inst2|74175:inst7|15 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.000 ns + " "Info: + Micro hold delay of destination is 1.000 ns" {  } { { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 184 352 416 264 "15" "" } } } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.300 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns a\[3\] 1 PIN PIN_45 2 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_45; Fanout = 2; PIN Node = 'a\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { a[3] } "NODE_NAME" } } { "full_multi.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/aaa/full_multi.bdf" { { -192 -40 128 -176 "a\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(1.200 ns) 5.600 ns mutli:inst\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\] 2 COMB LC6_F34 10 " "Info: 2: + IC(0.900 ns) + CELL(1.200 ns) = 5.600 ns; Loc. = LC6_F34; Fanout = 10; COMB Node = 'mutli:inst\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.100 ns" { a[3] mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.700 ns) 7.300 ns smdisplay:inst2\|74175:inst7\|15 3 REG LC2_F21 4 " "Info: 3: + IC(1.000 ns) + CELL(0.700 ns) = 7.300 ns; Loc. = LC2_F21; Fanout = 4; REG Node = 'smdisplay:inst2\|74175:inst7\|15'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.700 ns" { mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] smdisplay:inst2|74175:inst7|15 } "NODE_NAME" } } { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 184 352 416 264 "15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.400 ns ( 73.97 % ) " "Info: Total cell delay = 5.400 ns ( 73.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.900 ns ( 26.03 % ) " "Info: Total interconnect delay = 1.900 ns ( 26.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.300 ns" { a[3] mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] smdisplay:inst2|74175:inst7|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.300 ns" { a[3] a[3]~out mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] smdisplay:inst2|74175:inst7|15 } { 0.000ns 0.000ns 0.900ns 1.000ns } { 0.000ns 3.500ns 1.200ns 0.700ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { CLK smdisplay:inst2|74175:inst7|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { CLK CLK~out smdisplay:inst2|74175:inst7|15 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.300 ns" { a[3] mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] smdisplay:inst2|74175:inst7|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.300 ns" { a[3] a[3]~out mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] smdisplay:inst2|74175:inst7|15 } { 0.000ns 0.000ns 0.900ns 1.000ns } { 0.000ns 3.500ns 1.200ns 0.700ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Mar 24 15:42:28 2007 " "Info: Processing ended: Sat Mar 24 15:42:28 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}