📄 full_multi.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" { } { { "full_multi.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/aaa/full_multi.bdf" { { 144 128 296 160 "CLK" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLK" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "CLK " "Info: No valid register-to-register data paths exist for clock \"CLK\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "smdisplay:inst2\|74175:inst\|16 a\[0\] CLK 12.700 ns register " "Info: tsu for register \"smdisplay:inst2\|74175:inst\|16\" (data pin = \"a\[0\]\", clock pin = \"CLK\") is 12.700 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.900 ns + Longest pin register " "Info: + Longest pin to register delay is 13.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns a\[0\] 1 PIN PIN_53 2 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_53; Fanout = 2; PIN Node = 'a\[0\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { a[0] } "NODE_NAME" } } { "full_multi.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/aaa/full_multi.bdf" { { -192 -40 128 -176 "a\[3..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(0.500 ns) 5.500 ns mutli:inst\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\] 2 COMB LC3_F34 2 " "Info: 2: + IC(1.500 ns) + CELL(0.500 ns) = 5.500 ns; Loc. = LC3_F34; Fanout = 2; COMB Node = 'mutli:inst\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.000 ns" { a[0] mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 5.600 ns mutli:inst\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\] 3 COMB LC4_F34 2 " "Info: 3: + IC(0.000 ns) + CELL(0.100 ns) = 5.600 ns; Loc. = LC4_F34; Fanout = 2; COMB Node = 'mutli:inst\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.100 ns" { mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 5.700 ns mutli:inst\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] 4 COMB LC5_F34 2 " "Info: 4: + IC(0.000 ns) + CELL(0.100 ns) = 5.700 ns; Loc. = LC5_F34; Fanout = 2; COMB Node = 'mutli:inst\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.100 ns" { mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 6.700 ns mutli:inst\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\] 5 COMB LC6_F34 10 " "Info: 5: + IC(0.000 ns) + CELL(1.000 ns) = 6.700 ns; Loc. = LC6_F34; Fanout = 10; COMB Node = 'mutli:inst\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.000 ns" { mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.100 ns) 8.800 ns 74185:sys_74185\|25~4 6 COMB LC2_F23 3 " "Info: 6: + IC(1.000 ns) + CELL(1.100 ns) = 8.800 ns; Loc. = LC2_F23; Fanout = 3; COMB Node = '74185:sys_74185\|25~4'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.100 ns" { mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] 74185:sys_74185|25~4 } "NODE_NAME" } } { "74185.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74185.bdf" { { 1392 800 864 1496 "25" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.800 ns) 10.500 ns 74185:sys_74185\|41~305 7 COMB LC1_F28 1 " "Info: 7: + IC(0.900 ns) + CELL(0.800 ns) = 10.500 ns; Loc. = LC1_F28; Fanout = 1; COMB Node = '74185:sys_74185\|41~305'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.700 ns" { 74185:sys_74185|25~4 74185:sys_74185|41~305 } "NODE_NAME" } } { "74185.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74185.bdf" { { 496 960 1024 696 "41" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 11.300 ns 74185:sys_74185\|41~307 8 COMB LC2_F28 1 " "Info: 8: + IC(0.000 ns) + CELL(0.800 ns) = 11.300 ns; Loc. = LC2_F28; Fanout = 1; COMB Node = '74185:sys_74185\|41~307'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.800 ns" { 74185:sys_74185|41~305 74185:sys_74185|41~307 } "NODE_NAME" } } { "74185.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74185.bdf" { { 496 960 1024 696 "41" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 12.500 ns 74185:sys_74185\|41~298 9 COMB LC3_F28 1 " "Info: 9: + IC(0.000 ns) + CELL(1.200 ns) = 12.500 ns; Loc. = LC3_F28; Fanout = 1; COMB Node = '74185:sys_74185\|41~298'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.200 ns" { 74185:sys_74185|41~307 74185:sys_74185|41~298 } "NODE_NAME" } } { "74185.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74185.bdf" { { 496 960 1024 696 "41" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.500 ns) 13.900 ns smdisplay:inst2\|74175:inst\|16 10 REG LC4_F22 8 " "Info: 10: + IC(0.900 ns) + CELL(0.500 ns) = 13.900 ns; Loc. = LC4_F22; Fanout = 8; REG Node = 'smdisplay:inst2\|74175:inst\|16'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.400 ns" { 74185:sys_74185|41~298 smdisplay:inst2|74175:inst|16 } "NODE_NAME" } } { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 40 352 416 120 "16" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.600 ns ( 69.06 % ) " "Info: Total cell delay = 9.600 ns ( 69.06 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.300 ns ( 30.94 % ) " "Info: Total interconnect delay = 4.300 ns ( 30.94 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.900 ns" { a[0] mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] 74185:sys_74185|25~4 74185:sys_74185|41~305 74185:sys_74185|41~307 74185:sys_74185|41~298 smdisplay:inst2|74175:inst|16 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "13.900 ns" { a[0] a[0]~out mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] 74185:sys_74185|25~4 74185:sys_74185|41~305 74185:sys_74185|41~307 74185:sys_74185|41~298 smdisplay:inst2|74175:inst|16 } { 0.000ns 0.000ns 1.500ns 0.000ns 0.000ns 0.000ns 1.000ns 0.900ns 0.000ns 0.000ns 0.900ns } { 0.000ns 3.500ns 0.500ns 0.100ns 0.100ns 1.000ns 1.100ns 0.800ns 0.800ns 1.200ns 0.500ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" { } { { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 40 352 416 120 "16" "" } } } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.800 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK 1 CLK PIN_79 19 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 19; CLK Node = 'CLK'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "full_multi.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/aaa/full_multi.bdf" { { 144 128 296 160 "CLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.000 ns) 1.800 ns smdisplay:inst2\|74175:inst\|16 2 REG LC4_F22 8 " "Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC4_F22; Fanout = 8; REG Node = 'smdisplay:inst2\|74175:inst\|16'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { CLK smdisplay:inst2|74175:inst|16 } "NODE_NAME" } } { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 40 352 416 120 "16" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 83.33 % ) " "Info: Total cell delay = 1.500 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.300 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { CLK smdisplay:inst2|74175:inst|16 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { CLK CLK~out smdisplay:inst2|74175:inst|16 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.900 ns" { a[0] mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] 74185:sys_74185|25~4 74185:sys_74185|41~305 74185:sys_74185|41~307 74185:sys_74185|41~298 smdisplay:inst2|74175:inst|16 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "13.900 ns" { a[0] a[0]~out mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] 74185:sys_74185|25~4 74185:sys_74185|41~305 74185:sys_74185|41~307 74185:sys_74185|41~298 smdisplay:inst2|74175:inst|16 } { 0.000ns 0.000ns 1.500ns 0.000ns 0.000ns 0.000ns 1.000ns 0.900ns 0.000ns 0.000ns 0.900ns } { 0.000ns 3.500ns 0.500ns 0.100ns 0.100ns 1.000ns 1.100ns 0.800ns 0.800ns 1.200ns 0.500ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { CLK smdisplay:inst2|74175:inst|16 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { CLK CLK~out smdisplay:inst2|74175:inst|16 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK OF smdisplay:inst2\|74175:inst7\|16 14.600 ns register " "Info: tco from clock \"CLK\" to destination pin \"OF\" through register \"smdisplay:inst2\|74175:inst7\|16\" is 14.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 1.800 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK 1 CLK PIN_79 19 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 19; CLK Node = 'CLK'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "full_multi.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/aaa/full_multi.bdf" { { 144 128 296 160 "CLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.000 ns) 1.800 ns smdisplay:inst2\|74175:inst7\|16 2 REG LC1_F23 5 " "Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC1_F23; Fanout = 5; REG Node = 'smdisplay:inst2\|74175:inst7\|16'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { CLK smdisplay:inst2|74175:inst7|16 } "NODE_NAME" } } { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 40 352 416 120 "16" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 83.33 % ) " "Info: Total cell delay = 1.500 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.300 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { CLK smdisplay:inst2|74175:inst7|16 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { CLK CLK~out smdisplay:inst2|74175:inst7|16 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.400 ns + " "Info: + Micro clock to output delay of source is 0.400 ns" { } { { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 40 352 416 120 "16" "" } } } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.400 ns + Longest register pin " "Info: + Longest register to pin delay is 12.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns smdisplay:inst2\|74175:inst7\|16 1 REG LC1_F23 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_F23; Fanout = 5; REG Node = 'smdisplay:inst2\|74175:inst7\|16'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { smdisplay:inst2|74175:inst7|16 } "NODE_NAME" } } { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 40 352 416 120 "16" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.100 ns) 2.100 ns smdisplay:inst2\|74151:inst26\|f74151:sub\|67~129 2 COMB LC1_F35 2 " "Info: 2: + IC(1.000 ns) + CELL(1.100 ns) = 2.100 ns; Loc. = LC1_F35; Fanout = 2; COMB Node = 'smdisplay:inst2\|74151:inst26\|f74151:sub\|67~129'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.100 ns" { smdisplay:inst2|74175:inst7|16 smdisplay:inst2|74151:inst26|f74151:sub|67~129 } "NODE_NAME" } } { "f74151.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/f74151.bdf" { { 112 400 464 152 "67" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.200 ns) 4.700 ns smdisplay:inst2\|74151:inst26\|f74151:sub\|67~130 3 COMB LC4_F19 1 " "Info: 3: + IC(1.400 ns) + CELL(1.200 ns) = 4.700 ns; Loc. = LC4_F19; Fanout = 1; COMB Node = 'smdisplay:inst2\|74151:inst26\|f74151:sub\|67~130'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.600 ns" { smdisplay:inst2|74151:inst26|f74151:sub|67~129 smdisplay:inst2|74151:inst26|f74151:sub|67~130 } "NODE_NAME" } } { "f74151.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/f74151.bdf" { { 112 400 464 152 "67" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.200 ns) 6.100 ns smdisplay:inst2\|74151:inst26\|f74151:sub\|67~131 4 COMB LC7_F19 1 " "Info: 4: + IC(0.200 ns) + CELL(1.200 ns) = 6.100 ns; Loc. = LC7_F19; Fanout = 1; COMB Node = 'smdisplay:inst2\|74151:inst26\|f74151:sub\|67~131'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.400 ns" { smdisplay:inst2|74151:inst26|f74151:sub|67~130 smdisplay:inst2|74151:inst26|f74151:sub|67~131 } "NODE_NAME" } } { "f74151.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/f74151.bdf" { { 112 400 464 152 "67" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(4.600 ns) 12.400 ns OF 5 PIN PIN_15 0 " "Info: 5: + IC(1.700 ns) + CELL(4.600 ns) = 12.400 ns; Loc. = PIN_15; Fanout = 0; PIN Node = 'OF'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.300 ns" { smdisplay:inst2|74151:inst26|f74151:sub|67~131 OF } "NODE_NAME" } } { "full_multi.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/aaa/full_multi.bdf" { { 208 600 776 224 "OF" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.100 ns ( 65.32 % ) " "Info: Total cell delay = 8.100 ns ( 65.32 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.300 ns ( 34.68 % ) " "Info: Total interconnect delay = 4.300 ns ( 34.68 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.400 ns" { smdisplay:inst2|74175:inst7|16 smdisplay:inst2|74151:inst26|f74151:sub|67~129 smdisplay:inst2|74151:inst26|f74151:sub|67~130 smdisplay:inst2|74151:inst26|f74151:sub|67~131 OF } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.400 ns" { smdisplay:inst2|74175:inst7|16 smdisplay:inst2|74151:inst26|f74151:sub|67~129 smdisplay:inst2|74151:inst26|f74151:sub|67~130 smdisplay:inst2|74151:inst26|f74151:sub|67~131 OF } { 0.000ns 1.000ns 1.400ns 0.200ns 1.700ns } { 0.000ns 1.100ns 1.200ns 1.200ns 4.600ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { CLK smdisplay:inst2|74175:inst7|16 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { CLK CLK~out smdisplay:inst2|74175:inst7|16 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.400 ns" { smdisplay:inst2|74175:inst7|16 smdisplay:inst2|74151:inst26|f74151:sub|67~129 smdisplay:inst2|74151:inst26|f74151:sub|67~130 smdisplay:inst2|74151:inst26|f74151:sub|67~131 OF } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.400 ns" { smdisplay:inst2|74175:inst7|16 smdisplay:inst2|74151:inst26|f74151:sub|67~129 smdisplay:inst2|74151:inst26|f74151:sub|67~130 smdisplay:inst2|74151:inst26|f74151:sub|67~131 OF } { 0.000ns 1.000ns 1.400ns 0.200ns 1.700ns } { 0.000ns 1.100ns 1.200ns 1.200ns 4.600ns } } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "CLK OF 13.200 ns Longest " "Info: Longest tpd from source pin \"CLK\" to destination pin \"OF\" is 13.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK 1 CLK PIN_79 19 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 19; CLK Node = 'CLK'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "full_multi.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/aaa/full_multi.bdf" { { 144 128 296 160 "CLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.100 ns) 2.900 ns smdisplay:inst2\|74151:inst26\|f74151:sub\|67~129 2 COMB LC1_F35 2 " "Info: 2: + IC(0.300 ns) + CELL(1.100 ns) = 2.900 ns; Loc. = LC1_F35; Fanout = 2; COMB Node = 'smdisplay:inst2\|74151:inst26\|f74151:sub\|67~129'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK smdisplay:inst2|74151:inst26|f74151:sub|67~129 } "NODE_NAME" } } { "f74151.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/f74151.bdf" { { 112 400 464 152 "67" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.200 ns) 5.500 ns smdisplay:inst2\|74151:inst26\|f74151:sub\|67~130 3 COMB LC4_F19 1 " "Info: 3: + IC(1.400 ns) + CELL(1.200 ns) = 5.500 ns; Loc. = LC4_F19; Fanout = 1; COMB Node = 'smdisplay:inst2\|74151:inst26\|f74151:sub\|67~130'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.600 ns" { smdisplay:inst2|74151:inst26|f74151:sub|67~129 smdisplay:inst2|74151:inst26|f74151:sub|67~130 } "NODE_NAME" } } { "f74151.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/f74151.bdf" { { 112 400 464 152 "67" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.200 ns) 6.900 ns smdisplay:inst2\|74151:inst26\|f74151:sub\|67~131 4 COMB LC7_F19 1 " "Info: 4: + IC(0.200 ns) + CELL(1.200 ns) = 6.900 ns; Loc. = LC7_F19; Fanout = 1; COMB Node = 'smdisplay:inst2\|74151:inst26\|f74151:sub\|67~131'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.400 ns" { smdisplay:inst2|74151:inst26|f74151:sub|67~130 smdisplay:inst2|74151:inst26|f74151:sub|67~131 } "NODE_NAME" } } { "f74151.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/f74151.bdf" { { 112 400 464 152 "67" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(4.600 ns) 13.200 ns OF 5 PIN PIN_15 0 " "Info: 5: + IC(1.700 ns) + CELL(4.600 ns) = 13.200 ns; Loc. = PIN_15; Fanout = 0; PIN Node = 'OF'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.300 ns" { smdisplay:inst2|74151:inst26|f74151:sub|67~131 OF } "NODE_NAME" } } { "full_multi.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/aaa/full_multi.bdf" { { 208 600 776 224 "OF" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.600 ns ( 72.73 % ) " "Info: Total cell delay = 9.600 ns ( 72.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.600 ns ( 27.27 % ) " "Info: Total interconnect delay = 3.600 ns ( 27.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.200 ns" { CLK smdisplay:inst2|74151:inst26|f74151:sub|67~129 smdisplay:inst2|74151:inst26|f74151:sub|67~130 smdisplay:inst2|74151:inst26|f74151:sub|67~131 OF } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "13.200 ns" { CLK CLK~out smdisplay:inst2|74151:inst26|f74151:sub|67~129 smdisplay:inst2|74151:inst26|f74151:sub|67~130 smdisplay:inst2|74151:inst26|f74151:sub|67~131 OF } { 0.000ns 0.000ns 0.300ns 1.400ns 0.200ns 1.700ns } { 0.000ns 1.500ns 1.100ns 1.200ns 1.200ns 4.600ns } } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
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