📄 full_multi.tan.rpt
字号:
; N/A ; None ; 12.100 ns ; smdisplay:inst2|74175:inst|15 ; OA ; CLK ;
; N/A ; None ; 12.000 ns ; smdisplay:inst2|74175:inst|13 ; OF ; CLK ;
; N/A ; None ; 12.000 ns ; smdisplay:inst2|74175:inst|15 ; OE ; CLK ;
; N/A ; None ; 11.900 ns ; smdisplay:inst2|74175:inst|14 ; OF ; CLK ;
; N/A ; None ; 11.900 ns ; smdisplay:inst2|74175:inst|14 ; OE ; CLK ;
; N/A ; None ; 11.800 ns ; smdisplay:inst2|74175:inst|14 ; OG ; CLK ;
; N/A ; None ; 11.600 ns ; smdisplay:inst2|74175:inst|13 ; OG ; CLK ;
; N/A ; None ; 11.600 ns ; smdisplay:inst2|74175:inst|16 ; OE ; CLK ;
; N/A ; None ; 11.300 ns ; smdisplay:inst2|74175:inst7|16 ; OD ; CLK ;
; N/A ; None ; 11.300 ns ; smdisplay:inst2|74175:inst|13 ; OB ; CLK ;
; N/A ; None ; 11.300 ns ; smdisplay:inst2|74175:inst7|16 ; OB ; CLK ;
; N/A ; None ; 11.300 ns ; smdisplay:inst2|74175:inst7|16 ; OA ; CLK ;
; N/A ; None ; 11.200 ns ; smdisplay:inst2|74175:inst7|15 ; OD ; CLK ;
; N/A ; None ; 11.000 ns ; smdisplay:inst2|74175:inst|16 ; OG ; CLK ;
; N/A ; None ; 10.500 ns ; smdisplay:inst2|74175:inst|16 ; OA ; CLK ;
; N/A ; None ; 10.500 ns ; smdisplay:inst2|74175:inst|14 ; OA ; CLK ;
; N/A ; None ; 10.400 ns ; smdisplay:inst2|74175:inst7|15 ; OE ; CLK ;
; N/A ; None ; 10.200 ns ; smdisplay:inst2|74175:inst7|16 ; OE ; CLK ;
+-------+--------------+------------+--------------------------------+----+------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 13.200 ns ; CLK ; OF ;
; N/A ; None ; 13.000 ns ; CLK ; OG ;
; N/A ; None ; 12.200 ns ; CLK ; OB ;
; N/A ; None ; 11.400 ns ; CLK ; OA ;
; N/A ; None ; 11.300 ns ; CLK ; OD ;
; N/A ; None ; 11.000 ns ; CLK ; OE ;
; N/A ; None ; 8.800 ns ; CLK ; sel0 ;
; N/A ; None ; 8.300 ns ; CLK ; OC ;
+-------+-------------------+-----------------+------+------+
+--------------------------------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+------+--------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+------+--------------------------------+----------+
; N/A ; None ; -4.500 ns ; a[3] ; smdisplay:inst2|74175:inst7|15 ; CLK ;
; N/A ; None ; -4.500 ns ; a[3] ; smdisplay:inst2|74175:inst7|16 ; CLK ;
; N/A ; None ; -4.600 ns ; a[1] ; smdisplay:inst2|74175:inst7|16 ; CLK ;
; N/A ; None ; -4.600 ns ; a[3] ; smdisplay:inst2|74175:inst|15 ; CLK ;
; N/A ; None ; -4.600 ns ; a[3] ; smdisplay:inst2|74175:inst|13 ; CLK ;
; N/A ; None ; -4.600 ns ; a[2] ; smdisplay:inst2|74175:inst|14 ; CLK ;
; N/A ; None ; -4.700 ns ; a[2] ; smdisplay:inst2|74175:inst|15 ; CLK ;
; N/A ; None ; -4.700 ns ; a[2] ; smdisplay:inst2|74175:inst|13 ; CLK ;
; N/A ; None ; -4.700 ns ; a[2] ; smdisplay:inst2|74175:inst7|15 ; CLK ;
; N/A ; None ; -4.700 ns ; a[2] ; smdisplay:inst2|74175:inst7|16 ; CLK ;
; N/A ; None ; -4.800 ns ; a[1] ; smdisplay:inst2|74175:inst|15 ; CLK ;
; N/A ; None ; -4.800 ns ; a[1] ; smdisplay:inst2|74175:inst|13 ; CLK ;
; N/A ; None ; -4.800 ns ; a[1] ; smdisplay:inst2|74175:inst7|15 ; CLK ;
; N/A ; None ; -4.900 ns ; a[1] ; smdisplay:inst2|74175:inst|14 ; CLK ;
; N/A ; None ; -5.000 ns ; b[1] ; smdisplay:inst2|74175:inst7|16 ; CLK ;
; N/A ; None ; -5.000 ns ; b[3] ; smdisplay:inst2|74175:inst7|15 ; CLK ;
; N/A ; None ; -5.000 ns ; b[3] ; smdisplay:inst2|74175:inst7|16 ; CLK ;
; N/A ; None ; -5.000 ns ; b[2] ; smdisplay:inst2|74175:inst|14 ; CLK ;
; N/A ; None ; -5.200 ns ; b[3] ; smdisplay:inst2|74175:inst|15 ; CLK ;
; N/A ; None ; -5.200 ns ; b[3] ; smdisplay:inst2|74175:inst|13 ; CLK ;
; N/A ; None ; -5.200 ns ; b[2] ; smdisplay:inst2|74175:inst|15 ; CLK ;
; N/A ; None ; -5.200 ns ; b[2] ; smdisplay:inst2|74175:inst|13 ; CLK ;
; N/A ; None ; -5.200 ns ; b[2] ; smdisplay:inst2|74175:inst7|15 ; CLK ;
; N/A ; None ; -5.200 ns ; b[2] ; smdisplay:inst2|74175:inst7|16 ; CLK ;
; N/A ; None ; -5.300 ns ; b[1] ; smdisplay:inst2|74175:inst|15 ; CLK ;
; N/A ; None ; -5.300 ns ; b[1] ; smdisplay:inst2|74175:inst|13 ; CLK ;
; N/A ; None ; -5.300 ns ; b[1] ; smdisplay:inst2|74175:inst7|15 ; CLK ;
; N/A ; None ; -5.400 ns ; b[0] ; smdisplay:inst2|74175:inst|15 ; CLK ;
; N/A ; None ; -5.400 ns ; b[0] ; smdisplay:inst2|74175:inst|13 ; CLK ;
; N/A ; None ; -5.400 ns ; b[0] ; smdisplay:inst2|74175:inst7|15 ; CLK ;
; N/A ; None ; -5.400 ns ; b[0] ; smdisplay:inst2|74175:inst7|16 ; CLK ;
; N/A ; None ; -5.400 ns ; b[1] ; smdisplay:inst2|74175:inst|14 ; CLK ;
; N/A ; None ; -5.500 ns ; a[0] ; smdisplay:inst2|74175:inst|15 ; CLK ;
; N/A ; None ; -5.500 ns ; a[0] ; smdisplay:inst2|74175:inst|13 ; CLK ;
; N/A ; None ; -5.500 ns ; a[0] ; smdisplay:inst2|74175:inst7|15 ; CLK ;
; N/A ; None ; -5.500 ns ; a[0] ; smdisplay:inst2|74175:inst7|16 ; CLK ;
; N/A ; None ; -5.500 ns ; b[0] ; smdisplay:inst2|74175:inst|14 ; CLK ;
; N/A ; None ; -5.600 ns ; a[0] ; smdisplay:inst2|74175:inst|14 ; CLK ;
; N/A ; None ; -5.600 ns ; a[3] ; smdisplay:inst2|74175:inst|14 ; CLK ;
; N/A ; None ; -6.100 ns ; b[3] ; smdisplay:inst2|74175:inst|14 ; CLK ;
; N/A ; None ; -6.300 ns ; a[2] ; smdisplay:inst2|74175:inst|16 ; CLK ;
; N/A ; None ; -6.500 ns ; a[3] ; smdisplay:inst2|74175:inst|16 ; CLK ;
; N/A ; None ; -6.600 ns ; a[1] ; smdisplay:inst2|74175:inst|16 ; CLK ;
; N/A ; None ; -6.700 ns ; b[2] ; smdisplay:inst2|74175:inst|16 ; CLK ;
; N/A ; None ; -6.800 ns ; a[0] ; smdisplay:inst2|74175:inst|16 ; CLK ;
; N/A ; None ; -6.800 ns ; b[0] ; smdisplay:inst2|74175:inst|16 ; CLK ;
; N/A ; None ; -7.100 ns ; b[1] ; smdisplay:inst2|74175:inst|16 ; CLK ;
; N/A ; None ; -7.100 ns ; b[3] ; smdisplay:inst2|74175:inst|16 ; CLK ;
+---------------+-------------+-----------+------+--------------------------------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Sat Mar 24 15:42:27 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off full_multi -c full_multi
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "CLK" is an undefined clock
Info: No valid register-to-register data paths exist for clock "CLK"
Info: tsu for register "smdisplay:inst2|74175:inst|16" (data pin = "a[0]", clock pin = "CLK") is 12.700 ns
Info: + Longest pin to register delay is 13.900 ns
Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_53; Fanout = 2; PIN Node = 'a[0]'
Info: 2: + IC(1.500 ns) + CELL(0.500 ns) = 5.500 ns; Loc. = LC3_F34; Fanout = 2; COMB Node = 'mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0]'
Info: 3: + IC(0.000 ns) + CELL(0.100 ns) = 5.600 ns; Loc. = LC4_F34; Fanout = 2; COMB Node = 'mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1]'
Info: 4: + IC(0.000 ns) + CELL(0.100 ns) = 5.700 ns; Loc. = LC5_F34; Fanout = 2; COMB Node = 'mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2]'
Info: 5: + IC(0.000 ns) + CELL(1.000 ns) = 6.700 ns; Loc. = LC6_F34; Fanout = 10; COMB Node = 'mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]'
Info: 6: + IC(1.000 ns) + CELL(1.100 ns) = 8.800 ns; Loc. = LC2_F23; Fanout = 3; COMB Node = '74185:sys_74185|25~4'
Info: 7: + IC(0.900 ns) + CELL(0.800 ns) = 10.500 ns; Loc. = LC1_F28; Fanout = 1; COMB Node = '74185:sys_74185|41~305'
Info: 8: + IC(0.000 ns) + CELL(0.800 ns) = 11.300 ns; Loc. = LC2_F28; Fanout = 1; COMB Node = '74185:sys_74185|41~307'
Info: 9: + IC(0.000 ns) + CELL(1.200 ns) = 12.500 ns; Loc. = LC3_F28; Fanout = 1; COMB Node = '74185:sys_74185|41~298'
Info: 10: + IC(0.900 ns) + CELL(0.500 ns) = 13.900 ns; Loc. = LC4_F22; Fanout = 8; REG Node = 'smdisplay:inst2|74175:inst|16'
Info: Total cell delay = 9.600 ns ( 69.06 % )
Info: Total interconnect delay = 4.300 ns ( 30.94 % )
Info: + Micro setup delay of destination is 0.600 ns
Info: - Shortest clock path from clock "CLK" to destination register is 1.800 ns
Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 19; CLK Node = 'CLK'
Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC4_F22; Fanout = 8; REG Node = 'smdisplay:inst2|74175:inst|16'
Info: Total cell delay = 1.500 ns ( 83.33 % )
Info: Total interconnect delay = 0.300 ns ( 16.67 % )
Info: tco from clock "CLK" to destination pin "OF" through register "smdisplay:inst2|74175:inst7|16" is 14.600 ns
Info: + Longest clock path from clock "CLK" to source register is 1.800 ns
Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 19; CLK Node = 'CLK'
Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC1_F23; Fanout = 5; REG Node = 'smdisplay:inst2|74175:inst7|16'
Info: Total cell delay = 1.500 ns ( 83.33 % )
Info: Total interconnect delay = 0.300 ns ( 16.67 % )
Info: + Micro clock to output delay of source is 0.400 ns
Info: + Longest register to pin delay is 12.400 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_F23; Fanout = 5; REG Node = 'smdisplay:inst2|74175:inst7|16'
Info: 2: + IC(1.000 ns) + CELL(1.100 ns) = 2.100 ns; Loc. = LC1_F35; Fanout = 2; COMB Node = 'smdisplay:inst2|74151:inst26|f74151:sub|67~129'
Info: 3: + IC(1.400 ns) + CELL(1.200 ns) = 4.700 ns; Loc. = LC4_F19; Fanout = 1; COMB Node = 'smdisplay:inst2|74151:inst26|f74151:sub|67~130'
Info: 4: + IC(0.200 ns) + CELL(1.200 ns) = 6.100 ns; Loc. = LC7_F19; Fanout = 1; COMB Node = 'smdisplay:inst2|74151:inst26|f74151:sub|67~131'
Info: 5: + IC(1.700 ns) + CELL(4.600 ns) = 12.400 ns; Loc. = PIN_15; Fanout = 0; PIN Node = 'OF'
Info: Total cell delay = 8.100 ns ( 65.32 % )
Info: Total interconnect delay = 4.300 ns ( 34.68 % )
Info: Longest tpd from source pin "CLK" to destination pin "OF" is 13.200 ns
Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 19; CLK Node = 'CLK'
Info: 2: + IC(0.300 ns) + CELL(1.100 ns) = 2.900 ns; Loc. = LC1_F35; Fanout = 2; COMB Node = 'smdisplay:inst2|74151:inst26|f74151:sub|67~129'
Info: 3: + IC(1.400 ns) + CELL(1.200 ns) = 5.500 ns; Loc. = LC4_F19; Fanout = 1; COMB Node = 'smdisplay:inst2|74151:inst26|f74151:sub|67~130'
Info: 4: + IC(0.200 ns) + CELL(1.200 ns) = 6.900 ns; Loc. = LC7_F19; Fanout = 1; COMB Node = 'smdisplay:inst2|74151:inst26|f74151:sub|67~131'
Info: 5: + IC(1.700 ns) + CELL(4.600 ns) = 13.200 ns; Loc. = PIN_15; Fanout = 0; PIN Node = 'OF'
Info: Total cell delay = 9.600 ns ( 72.73 % )
Info: Total interconnect delay = 3.600 ns ( 27.27 % )
Info: th for register "smdisplay:inst2|74175:inst7|15" (data pin = "a[3]", clock pin = "CLK") is -4.500 ns
Info: + Longest clock path from clock "CLK" to destination register is 1.800 ns
Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 19; CLK Node = 'CLK'
Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC2_F21; Fanout = 4; REG Node = 'smdisplay:inst2|74175:inst7|15'
Info: Total cell delay = 1.500 ns ( 83.33 % )
Info: Total interconnect delay = 0.300 ns ( 16.67 % )
Info: + Micro hold delay of destination is 1.000 ns
Info: - Shortest pin to register delay is 7.300 ns
Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_45; Fanout = 2; PIN Node = 'a[3]'
Info: 2: + IC(0.900 ns) + CELL(1.200 ns) = 5.600 ns; Loc. = LC6_F34; Fanout = 10; COMB Node = 'mutli:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]'
Info: 3: + IC(1.000 ns) + CELL(0.700 ns) = 7.300 ns; Loc. = LC2_F21; Fanout = 4; REG Node = 'smdisplay:inst2|74175:inst7|15'
Info: Total cell delay = 5.400 ns ( 73.97 % )
Info: Total interconnect delay = 1.900 ns ( 26.03 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Sat Mar 24 15:42:28 2007
Info: Elapsed time: 00:00:01
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