mult_99.tan.qmsg

一些很好的FPGA设计实例

{ "Info" "ITDB_FULL_TPD_RESULT" "address\[7\] A 17.600 ns Longest " "Info: Longest tpd from source pin \"address\[7\]\" to destination pin \"A\" is 17.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns address\[7\] 1 PIN PIN_45 14 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_45; Fanout = 14; PIN Node = 'address\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { address[7] } "NODE_NAME" } } { "mult_99.bdf" "" { Schematic "C:/altera/ym/text7/mult_99.bdf" { { 24 80 248 40 "address\[7..0\]" "" } { 272 8 272 288 "address\[4\]" "" } { 288 8 272 304 "address\[5\]" "" } { 304 8 272 320 "address\[6\]" "" } { 320 8 272 336 "address\[7\]" "" } { 104 8 272 120 "address\[0\]" "" } { 32 256 272 120 "address\[7..0\]" "" } { 120 8 272 136 "address\[1\]" "" } { 136 8 272 152 "address\[2\]" "" } { 152 8 272 168 "address\[3\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(0.900 ns) 7.500 ns 74153M:inst12\|9~778 2 COMB LC8_B21 2 " "Info: 2: + IC(3.100 ns) + CELL(0.900 ns) = 7.500 ns; Loc. = LC8_B21; Fanout = 2; COMB Node = '74153M:inst12\|9~778'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.000 ns" { address[7] 74153M:inst12|9~778 } "NODE_NAME" } } { "74153M.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74153M.bdf" { { 200 600 664 272 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.900 ns) 8.600 ns 74153M:inst12\|9~779 3 COMB LC1_B21 1 " "Info: 3: + IC(0.200 ns) + CELL(0.900 ns) = 8.600 ns; Loc. = LC1_B21; Fanout = 1; COMB Node = '74153M:inst12\|9~779'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.100 ns" { 74153M:inst12|9~778 74153M:inst12|9~779 } "NODE_NAME" } } { "74153M.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74153M.bdf" { { 200 600 664 272 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.900 ns) 10.500 ns 74153M:inst12\|9~787 4 COMB LC7_B28 1 " "Info: 4: + IC(1.000 ns) + CELL(0.900 ns) = 10.500 ns; Loc. = LC7_B28; Fanout = 1; COMB Node = '74153M:inst12\|9~787'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { 74153M:inst12|9~779 74153M:inst12|9~787 } "NODE_NAME" } } { "74153M.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74153M.bdf" { { 200 600 664 272 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.900 ns) 11.600 ns 74153M:inst12\|9~763 5 COMB LC5_B28 1 " "Info: 5: + IC(0.200 ns) + CELL(0.900 ns) = 11.600 ns; Loc. = LC5_B28; Fanout = 1; COMB Node = '74153M:inst12\|9~763'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.100 ns" { 74153M:inst12|9~787 74153M:inst12|9~763 } "NODE_NAME" } } { "74153M.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74153M.bdf" { { 200 600 664 272 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(4.600 ns) 17.600 ns A 6 PIN PIN_10 0 " "Info: 6: + IC(1.400 ns) + CELL(4.600 ns) = 17.600 ns; Loc. = PIN_10; Fanout = 0; PIN Node = 'A'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.000 ns" { 74153M:inst12|9~763 A } "NODE_NAME" } } { "mult_99.bdf" "" { Schematic "C:/altera/ym/text7/mult_99.bdf" { { 592 984 1000 768 "A" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.700 ns ( 66.48 % ) " "Info: Total cell delay = 11.700 ns ( 66.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.900 ns ( 33.52 % ) " "Info: Total interconnect delay = 5.900 ns ( 33.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "17.600 ns" { address[7] 74153M:inst12|9~778 74153M:inst12|9~779 74153M:inst12|9~787 74153M:inst12|9~763 A } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "17.600 ns" { address[7] address[7]~out 74153M:inst12|9~778 74153M:inst12|9~779 74153M:inst12|9~787 74153M:inst12|9~763 A } { 0.000ns 0.000ns 3.100ns 0.200ns 1.000ns 0.200ns 1.400ns } { 0.000ns 3.500ns 0.900ns 0.900ns 0.900ns 0.900ns 4.600ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "lpm_rom:inst\|altrom:srom\|q\[0\]~reg_ra0 address\[0\] clk -4.800 ns memory " "Info: th for memory \"lpm_rom:inst\|altrom:srom\|q\[0\]~reg_ra0\" (data pin = \"address\[0\]\", clock pin = \"clk\") is -4.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.800 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to destination memory is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_79 65 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 65; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mult_99.bdf" "" { Schematic "C:/altera/ym/text7/mult_99.bdf" { { 40 80 248 56 "clk" "" } { 712 -336 -272 728 "clk" "" } { 32 248 344 48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.000 ns) 1.800 ns lpm_rom:inst\|altrom:srom\|q\[0\]~reg_ra0 2 MEM EC12_B 1 " "Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = EC12_B; Fanout = 1; MEM Node = 'lpm_rom:inst\|altrom:srom\|q\[0\]~reg_ra0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { clk lpm_rom:inst|altrom:srom|q[0]~reg_ra0 } "NODE_NAME" } } { "altrom.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 83.33 % ) " "Info: Total cell delay = 1.500 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.300 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { clk lpm_rom:inst|altrom:srom|q[0]~reg_ra0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { clk clk~out lpm_rom:inst|altrom:srom|q[0]~reg_ra0 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.400 ns + " "Info: + Micro hold delay of destination is 0.400 ns" {  } { { "altrom.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.000 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 7.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns address\[0\] 1 PIN PIN_57 17 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_57; Fanout = 17; PIN Node = 'address\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { address[0] } "NODE_NAME" } } { "mult_99.bdf" "" { Schematic "C:/altera/ym/text7/mult_99.bdf" { { 24 80 248 40 "address\[7..0\]" "" } { 272 8 272 288 "address\[4\]" "" } { 288 8 272 304 "address\[5\]" "" } { 304 8 272 320 "address\[6\]" "" } { 320 8 272 336 "address\[7\]" "" } { 104 8 272 120 "address\[0\]" "" } { 32 256 272 120 "address\[7..0\]" "" } { 120 8 272 136 "address\[1\]" "" } { 136 8 272 152 "address\[2\]" "" } { 152 8 272 168 "address\[3\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(0.700 ns) 7.000 ns lpm_rom:inst\|altrom:srom\|q\[0\]~reg_ra0 2 MEM EC12_B 1 " "Info: 2: + IC(2.800 ns) + CELL(0.700 ns) = 7.000 ns; Loc. = EC12_B; Fanout = 1; MEM Node = 'lpm_rom:inst\|altrom:srom\|q\[0\]~reg_ra0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.500 ns" { address[0] lpm_rom:inst|altrom:srom|q[0]~reg_ra0 } "NODE_NAME" } } { "altrom.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.200 ns ( 60.00 % ) " "Info: Total cell delay = 4.200 ns ( 60.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns ( 40.00 % ) " "Info: Total interconnect delay = 2.800 ns ( 40.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.000 ns" { address[0] lpm_rom:inst|altrom:srom|q[0]~reg_ra0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.000 ns" { address[0] address[0]~out lpm_rom:inst|altrom:srom|q[0]~reg_ra0 } { 0.000ns 0.000ns 2.800ns } { 0.000ns 3.500ns 0.700ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { clk lpm_rom:inst|altrom:srom|q[0]~reg_ra0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { clk clk~out lpm_rom:inst|altrom:srom|q[0]~reg_ra0 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.000 ns" { address[0] lpm_rom:inst|altrom:srom|q[0]~reg_ra0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.000 ns" { address[0] address[0]~out lpm_rom:inst|altrom:srom|q[0]~reg_ra0 } { 0.000ns 0.000ns 2.800ns } { 0.000ns 3.500ns 0.700ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 09 02:58:18 2007 " "Info: Processing ended: Fri Feb 09 02:58:18 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}