mult_99.tan.qmsg

一些很好的FPGA设计实例

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "mult_99.bdf" "" { Schematic "C:/altera/ym/text7/mult_99.bdf" { { 40 80 248 56 "clk" "" } { 712 -336 -272 728 "clk" "" } { 32 248 344 48 "clk" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "7493:inst39\|16 " "Info: Detected ripple clock \"7493:inst39\|16\" as buffer" {  } { { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 48 480 544 128 "16" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "7493:inst39\|16" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register 7493:inst39\|15 7493:inst39\|15 200.0 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 200.0 MHz between source register \"7493:inst39\|15\" and destination register \"7493:inst39\|15\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.700 ns + Longest register register " "Info: + Longest register to register delay is 0.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 7493:inst39\|15 1 REG LC3_F31 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_F31; Fanout = 13; REG Node = '7493:inst39\|15'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { 7493:inst39|15 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.500 ns) 0.700 ns 7493:inst39\|15 2 REG LC3_F31 13 " "Info: 2: + IC(0.200 ns) + CELL(0.500 ns) = 0.700 ns; Loc. = LC3_F31; Fanout = 13; REG Node = '7493:inst39\|15'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.700 ns" { 7493:inst39|15 7493:inst39|15 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 71.43 % ) " "Info: Total cell delay = 0.500 ns ( 71.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns ( 28.57 % ) " "Info: Total interconnect delay = 0.200 ns ( 28.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.700 ns" { 7493:inst39|15 7493:inst39|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "0.700 ns" { 7493:inst39|15 7493:inst39|15 } { 0.000ns 0.200ns } { 0.000ns 0.500ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.700 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 5.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_79 65 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 65; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mult_99.bdf" "" { Schematic "C:/altera/ym/text7/mult_99.bdf" { { 40 80 248 56 "clk" "" } { 712 -336 -272 728 "clk" "" } { 32 248 344 48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.400 ns) 2.200 ns 7493:inst39\|16 2 REG LC1_C17 30 " "Info: 2: + IC(0.300 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC1_C17; Fanout = 30; REG Node = '7493:inst39\|16'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.700 ns" { clk 7493:inst39|16 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 48 480 544 128 "16" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(0.000 ns) 5.700 ns 7493:inst39\|15 3 REG LC3_F31 13 " "Info: 3: + IC(3.500 ns) + CELL(0.000 ns) = 5.700 ns; Loc. = LC3_F31; Fanout = 13; REG Node = '7493:inst39\|15'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.500 ns" { 7493:inst39|16 7493:inst39|15 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 33.33 % ) " "Info: Total cell delay = 1.900 ns ( 33.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.800 ns ( 66.67 % ) " "Info: Total interconnect delay = 3.800 ns ( 66.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.700 ns" { clk 7493:inst39|16 7493:inst39|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.700 ns" { clk clk~out 7493:inst39|16 7493:inst39|15 } { 0.000ns 0.000ns 0.300ns 3.500ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.700 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 5.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_79 65 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 65; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mult_99.bdf" "" { Schematic "C:/altera/ym/text7/mult_99.bdf" { { 40 80 248 56 "clk" "" } { 712 -336 -272 728 "clk" "" } { 32 248 344 48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.400 ns) 2.200 ns 7493:inst39\|16 2 REG LC1_C17 30 " "Info: 2: + IC(0.300 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC1_C17; Fanout = 30; REG Node = '7493:inst39\|16'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.700 ns" { clk 7493:inst39|16 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 48 480 544 128 "16" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(0.000 ns) 5.700 ns 7493:inst39\|15 3 REG LC3_F31 13 " "Info: 3: + IC(3.500 ns) + CELL(0.000 ns) = 5.700 ns; Loc. = LC3_F31; Fanout = 13; REG Node = '7493:inst39\|15'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.500 ns" { 7493:inst39|16 7493:inst39|15 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 33.33 % ) " "Info: Total cell delay = 1.900 ns ( 33.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.800 ns ( 66.67 % ) " "Info: Total interconnect delay = 3.800 ns ( 66.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.700 ns" { clk 7493:inst39|16 7493:inst39|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.700 ns" { clk clk~out 7493:inst39|16 7493:inst39|15 } { 0.000ns 0.000ns 0.300ns 3.500ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.700 ns" { clk 7493:inst39|16 7493:inst39|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.700 ns" { clk clk~out 7493:inst39|16 7493:inst39|15 } { 0.000ns 0.000ns 0.300ns 3.500ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.700 ns" { clk 7493:inst39|16 7493:inst39|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.700 ns" { clk clk~out 7493:inst39|16 7493:inst39|15 } { 0.000ns 0.000ns 0.300ns 3.500ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.400 ns + " "Info: + Micro clock to output delay of source is 0.400 ns" {  } { { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.700 ns" { 7493:inst39|15 7493:inst39|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "0.700 ns" { 7493:inst39|15 7493:inst39|15 } { 0.000ns 0.200ns } { 0.000ns 0.500ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.700 ns" { clk 7493:inst39|16 7493:inst39|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.700 ns" { clk clk~out 7493:inst39|16 7493:inst39|15 } { 0.000ns 0.000ns 0.300ns 3.500ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.700 ns" { clk 7493:inst39|16 7493:inst39|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.700 ns" { clk clk~out 7493:inst39|16 7493:inst39|15 } { 0.000ns 0.000ns 0.300ns 3.500ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { 7493:inst39|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { 7493:inst39|15 } {  } {  } } } { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "lpm_rom:inst\|altrom:srom\|q\[3\]~reg_ra7 address\[7\] clk 7.200 ns memory " "Info: tsu for memory \"lpm_rom:inst\|altrom:srom\|q\[3\]~reg_ra7\" (data pin = \"address\[7\]\", clock pin = \"clk\") is 7.200 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest pin memory " "Info: + Longest pin to memory delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns address\[7\] 1 PIN PIN_45 14 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_45; Fanout = 14; PIN Node = 'address\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { address[7] } "NODE_NAME" } } { "mult_99.bdf" "" { Schematic "C:/altera/ym/text7/mult_99.bdf" { { 24 80 248 40 "address\[7..0\]" "" } { 272 8 272 288 "address\[4\]" "" } { 288 8 272 304 "address\[5\]" "" } { 304 8 272 320 "address\[6\]" "" } { 320 8 272 336 "address\[7\]" "" } { 104 8 272 120 "address\[0\]" "" } { 32 256 272 120 "address\[7..0\]" "" } { 120 8 272 136 "address\[1\]" "" } { 136 8 272 152 "address\[2\]" "" } { 152 8 272 168 "address\[3\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.800 ns) + CELL(0.700 ns) 8.000 ns lpm_rom:inst\|altrom:srom\|q\[3\]~reg_ra7 2 MEM EC4_B 1 " "Info: 2: + IC(3.800 ns) + CELL(0.700 ns) = 8.000 ns; Loc. = EC4_B; Fanout = 1; MEM Node = 'lpm_rom:inst\|altrom:srom\|q\[3\]~reg_ra7'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.500 ns" { address[7] lpm_rom:inst|altrom:srom|q[3]~reg_ra7 } "NODE_NAME" } } { "altrom.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.200 ns ( 52.50 % ) " "Info: Total cell delay = 4.200 ns ( 52.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.800 ns ( 47.50 % ) " "Info: Total interconnect delay = 3.800 ns ( 47.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.000 ns" { address[7] lpm_rom:inst|altrom:srom|q[3]~reg_ra7 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.000 ns" { address[7] address[7]~out lpm_rom:inst|altrom:srom|q[3]~reg_ra7 } { 0.000ns 0.000ns 3.800ns } { 0.000ns 3.500ns 0.700ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" {  } { { "altrom.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.800 ns - Shortest memory " "Info: - Shortest clock path from clock \"clk\" to destination memory is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_79 65 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 65; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mult_99.bdf" "" { Schematic "C:/altera/ym/text7/mult_99.bdf" { { 40 80 248 56 "clk" "" } { 712 -336 -272 728 "clk" "" } { 32 248 344 48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.000 ns) 1.800 ns lpm_rom:inst\|altrom:srom\|q\[3\]~reg_ra7 2 MEM EC4_B 1 " "Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = EC4_B; Fanout = 1; MEM Node = 'lpm_rom:inst\|altrom:srom\|q\[3\]~reg_ra7'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { clk lpm_rom:inst|altrom:srom|q[3]~reg_ra7 } "NODE_NAME" } } { "altrom.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 83.33 % ) " "Info: Total cell delay = 1.500 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.300 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { clk lpm_rom:inst|altrom:srom|q[3]~reg_ra7 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { clk clk~out lpm_rom:inst|altrom:srom|q[3]~reg_ra7 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.000 ns" { address[7] lpm_rom:inst|altrom:srom|q[3]~reg_ra7 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.000 ns" { address[7] address[7]~out lpm_rom:inst|altrom:srom|q[3]~reg_ra7 } { 0.000ns 0.000ns 3.800ns } { 0.000ns 3.500ns 0.700ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { clk lpm_rom:inst|altrom:srom|q[3]~reg_ra7 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { clk clk~out lpm_rom:inst|altrom:srom|q[3]~reg_ra7 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk B lpm_rom:inst\|altrom:srom\|q\[1\]~reg_ra0 20.100 ns memory " "Info: tco from clock \"clk\" to destination pin \"B\" through memory \"lpm_rom:inst\|altrom:srom\|q\[1\]~reg_ra0\" is 20.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.800 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to source memory is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_79 65 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 65; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mult_99.bdf" "" { Schematic "C:/altera/ym/text7/mult_99.bdf" { { 40 80 248 56 "clk" "" } { 712 -336 -272 728 "clk" "" } { 32 248 344 48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.000 ns) 1.800 ns lpm_rom:inst\|altrom:srom\|q\[1\]~reg_ra0 2 MEM EC3_B 1 " "Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = EC3_B; Fanout = 1; MEM Node = 'lpm_rom:inst\|altrom:srom\|q\[1\]~reg_ra0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { clk lpm_rom:inst|altrom:srom|q[1]~reg_ra0 } "NODE_NAME" } } { "altrom.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 83.33 % ) " "Info: Total cell delay = 1.500 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.300 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { clk lpm_rom:inst|altrom:srom|q[1]~reg_ra0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { clk clk~out lpm_rom:inst|altrom:srom|q[1]~reg_ra0 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns + " "Info: + Micro clock to output delay of source is 0.300 ns" {  } { { "altrom.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "18.000 ns + Longest memory pin " "Info: + Longest memory to pin delay is 18.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_rom:inst\|altrom:srom\|q\[1\]~reg_ra0 1 MEM EC3_B 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = EC3_B; Fanout = 1; MEM Node = 'lpm_rom:inst\|altrom:srom\|q\[1\]~reg_ra0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_rom:inst|altrom:srom|q[1]~reg_ra0 } "NODE_NAME" } } { "altrom.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.800 ns) 3.800 ns lpm_rom:inst\|altrom:srom\|q\[1\]~mem_cell_ra0 2 MEM EC3_B 1 " "Info: 2: + IC(0.000 ns) + CELL(3.800 ns) = 3.800 ns; Loc. = EC3_B; Fanout = 1; MEM Node = 'lpm_rom:inst\|altrom:srom\|q\[1\]~mem_cell_ra0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.800 ns" { lpm_rom:inst|altrom:srom|q[1]~reg_ra0 lpm_rom:inst|altrom:srom|q[1]~mem_cell_ra0 } "NODE_NAME" } } { "altrom.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 5.000 ns lpm_rom:inst\|altrom:srom\|q\[1\] 3 MEM EC3_B 10 " "Info: 3: + IC(0.000 ns) + CELL(1.200 ns) = 5.000 ns; Loc. = EC3_B; Fanout = 10; MEM Node = 'lpm_rom:inst\|altrom:srom\|q\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.200 ns" { lpm_rom:inst|altrom:srom|q[1]~mem_cell_ra0 lpm_rom:inst|altrom:srom|q[1] } "NODE_NAME" } } { "altrom.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(1.100 ns) 7.800 ns 74153M:inst7\|9~826 4 COMB LC6_B34 1 " "Info: 4: + IC(1.700 ns) + CELL(1.100 ns) = 7.800 ns; Loc. = LC6_B34; Fanout = 1; COMB Node = '74153M:inst7\|9~826'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.800 ns" { lpm_rom:inst|altrom:srom|q[1] 74153M:inst7|9~826 } "NODE_NAME" } } { "74153M.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74153M.bdf" { { 200 600 664 272 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(1.100 ns) 9.800 ns 74153M:inst10\|9~886 5 COMB LC8_B32 1 " "Info: 5: + IC(0.900 ns) + CELL(1.100 ns) = 9.800 ns; Loc. = LC8_B32; Fanout = 1; COMB Node = '74153M:inst10\|9~886'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.000 ns" { 74153M:inst7|9~826 74153M:inst10|9~886 } "NODE_NAME" } } { "74153M.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74153M.bdf" { { 200 600 664 272 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.100 ns) 11.900 ns 74153M:inst10\|9~865 6 COMB LC7_B21 1 " "Info: 6: + IC(1.000 ns) + CELL(1.100 ns) = 11.900 ns; Loc. = LC7_B21; Fanout = 1; COMB Node = '74153M:inst10\|9~865'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.100 ns" { 74153M:inst10|9~886 74153M:inst10|9~865 } "NODE_NAME" } } { "74153M.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74153M.bdf" { { 200 600 664 272 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(4.600 ns) 18.000 ns B 7 PIN PIN_11 0 " "Info: 7: + IC(1.500 ns) + CELL(4.600 ns) = 18.000 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'B'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { 74153M:inst10|9~865 B } "NODE_NAME" } } { "mult_99.bdf" "" { Schematic "C:/altera/ym/text7/mult_99.bdf" { { 592 840 856 768 "B" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.900 ns ( 71.67 % ) " "Info: Total cell delay = 12.900 ns ( 71.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.100 ns ( 28.33 % ) " "Info: Total interconnect delay = 5.100 ns ( 28.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "18.000 ns" { lpm_rom:inst|altrom:srom|q[1]~reg_ra0 lpm_rom:inst|altrom:srom|q[1]~mem_cell_ra0 lpm_rom:inst|altrom:srom|q[1] 74153M:inst7|9~826 74153M:inst10|9~886 74153M:inst10|9~865 B } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "18.000 ns" { lpm_rom:inst|altrom:srom|q[1]~reg_ra0 lpm_rom:inst|altrom:srom|q[1]~mem_cell_ra0 lpm_rom:inst|altrom:srom|q[1] 74153M:inst7|9~826 74153M:inst10|9~886 74153M:inst10|9~865 B } { 0.000ns 0.000ns 0.000ns 1.700ns 0.900ns 1.000ns 1.500ns } { 0.000ns 3.800ns 1.200ns 1.100ns 1.100ns 1.100ns 4.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { clk lpm_rom:inst|altrom:srom|q[1]~reg_ra0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { clk clk~out lpm_rom:inst|altrom:srom|q[1]~reg_ra0 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "18.000 ns" { lpm_rom:inst|altrom:srom|q[1]~reg_ra0 lpm_rom:inst|altrom:srom|q[1]~mem_cell_ra0 lpm_rom:inst|altrom:srom|q[1] 74153M:inst7|9~826 74153M:inst10|9~886 74153M:inst10|9~865 B } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "18.000 ns" { lpm_rom:inst|altrom:srom|q[1]~reg_ra0 lpm_rom:inst|altrom:srom|q[1]~mem_cell_ra0 lpm_rom:inst|altrom:srom|q[1] 74153M:inst7|9~826 74153M:inst10|9~886 74153M:inst10|9~865 B } { 0.000ns 0.000ns 0.000ns 1.700ns 0.900ns 1.000ns 1.500ns } { 0.000ns 3.800ns 1.200ns 1.100ns 1.100ns 1.100ns 4.600ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}