gift2.tan.qmsg

一些很好的FPGA设计实例

{ "Info" "ITDB_FULL_TCO_RESULT" "clk2 y\[3\] lpm_counter:y_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 9.200 ns register " "Info: tco from clock \"clk2\" to destination pin \"y\[3\]\" through register \"lpm_counter:y_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]\" is 9.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk2 source 1.800 ns + Longest register " "Info: + Longest clock path from clock \"clk2\" to source register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk2 1 CLK PIN_183 19 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_183; Fanout = 19; CLK Node = 'clk2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk2 } "NODE_NAME" } } { "gift2.v" "" { Text "E:/altera/others/gift2/gift2.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.000 ns) 1.800 ns lpm_counter:y_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC7_E10 11 " "Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC7_E10; Fanout = 11; REG Node = 'lpm_counter:y_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { clk2 lpm_counter:y_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 83.33 % ) " "Info: Total cell delay = 1.500 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.300 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { clk2 lpm_counter:y_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { clk2 clk2~out lpm_counter:y_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.400 ns + " "Info: + Micro clock to output delay of source is 0.400 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.000 ns + Longest register pin " "Info: + Longest register to pin delay is 7.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:y_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 1 REG LC7_E10 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_E10; Fanout = 11; REG Node = 'lpm_counter:y_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_counter:y_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.900 ns) 1.900 ns y\[3\]~12 2 COMB LC4_E5 1 " "Info: 2: + IC(1.000 ns) + CELL(0.900 ns) = 1.900 ns; Loc. = LC4_E5; Fanout = 1; COMB Node = 'y\[3\]~12'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { lpm_counter:y_rtl_0|alt_counter_f10ke:wysi_counter|q[3] y[3]~12 } "NODE_NAME" } } { "gift2.v" "" { Text "E:/altera/others/gift2/gift2.v" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(4.600 ns) 7.000 ns y\[3\] 3 PIN PIN_99 0 " "Info: 3: + IC(0.500 ns) + CELL(4.600 ns) = 7.000 ns; Loc. = PIN_99; Fanout = 0; PIN Node = 'y\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.100 ns" { y[3]~12 y[3] } "NODE_NAME" } } { "gift2.v" "" { Text "E:/altera/others/gift2/gift2.v" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns ( 78.57 % ) " "Info: Total cell delay = 5.500 ns ( 78.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns ( 21.43 % ) " "Info: Total interconnect delay = 1.500 ns ( 21.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.000 ns" { lpm_counter:y_rtl_0|alt_counter_f10ke:wysi_counter|q[3] y[3]~12 y[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.000 ns" { lpm_counter:y_rtl_0|alt_counter_f10ke:wysi_counter|q[3] y[3]~12 y[3] } { 0.000ns 1.000ns 0.500ns } { 0.000ns 0.900ns 4.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { clk2 lpm_counter:y_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { clk2 clk2~out lpm_counter:y_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.000 ns" { lpm_counter:y_rtl_0|alt_counter_f10ke:wysi_counter|q[3] y[3]~12 y[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.000 ns" { lpm_counter:y_rtl_0|alt_counter_f10ke:wysi_counter|q[3] y[3]~12 y[3] } { 0.000ns 1.000ns 0.500ns } { 0.000ns 0.900ns 4.600ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 30 21:53:07 2007 " "Info: Processing ended: Fri Mar 30 21:53:07 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}