gift2.v

来自「一些很好的FPGA设计实例」· Verilog 代码 · 共 86 行

module gift2(y,c,clk1,clk2);
output[3:0] y;
output[15:0] c; 
input clk1,clk2;
reg[3:0] y;
reg[15:0] c;
integer i=1;
always @(posedge clk1)
 begin
  if(i==3)
   i=1;
  else
   i=i+1;
 end
always @(posedge clk2)
 begin
    y=y+1;
  if(i==1)
   begin
    case(y)
    0: c= 16'b0;
    1: c= 16'b0;
    2: c= 16'b0;
    3: c= 16'b0;
    4: c= 16'b0;
    5: c= 16'b0011_0000_0000_1100;
    6: c= 16'b0011_0000_0000_1100;
    7: c= 16'b0011_1111_1111_1100;
    8: c= 16'b0011_1111_1111_1100;
    9: c= 16'b0011_0000_0000_1100;
    10: c= 16'b0011_0000_0000_1100;
    11: c= 16'b0;
    12: c= 16'b0;
    13: c= 16'b0;
    14: c= 16'b0;
    15: c= 16'b0;
    default: c= 16'b0;
    endcase
   end
  else if(i==2) 
   begin
    case(y)
    0: c= 16'b0;
    1: c= 16'b0;
    2: c= 16'b0000_0000_0111_0000;
    3: c= 16'b0000_0000_1111_1000;
    4: c= 16'b0000_0001_1111_1100;
    5: c= 16'b0000_0011_1111_1100;
    6: c= 16'b0000_0111_1111_1000;
    7: c= 16'b0000_1111_1111_0000;
    8: c= 16'b0000_1111_1111_0000;
    9: c= 16'b0000_0111_1111_1000;
    10: c= 16'b0000_0011_1111_1100;
    11: c= 16'b0000_0001_1111_1100;
    12: c= 16'b0000_0000_1111_1000;
    13: c= 16'b0000_0000_0111_0000;
    14: c= 16'b0;
    15: c= 16'b0;
    default: c= 16'b0;
    endcase
   end
  else if(i==3) 
   begin
    case(y)
    0: c= 16'b0;
    1: c= 16'b0;
    2: c= 16'b0;
    3: c= 16'b0000_0111_1111_1100;
    4: c= 16'b0000_1111_1111_1100;
    5: c= 16'b0001_1000_0000_0000;
    6: c= 16'b0011_0000_0000_0000;
    7: c= 16'b0011_0000_0000_0000;
    8: c= 16'b0011_0000_0000_0000;
    9: c= 16'b0011_0000_0000_0000;
    10: c= 16'b0001_1000_0000_0000;
    11: c= 16'b0000_1111_1111_1100;
    12: c= 16'b0000_0111_1111_1100;
    13: c= 16'b0;
    14: c= 16'b0;
    15: c= 16'b0;
    default: c= 16'b0;
    endcase
   end
 end
endmodule