control.map.rpt

一些很好的FPGA设计实例

+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 62    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 30    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------+
; Source assignments for Top-level Entity: |control ;
+----------------+-------+------+-------------------+
; Assignment     ; Value ; From ; To                ;
+----------------+-------+------+-------------------+
; POWER_UP_LEVEL ; Low   ; -    ; always0~          ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~          ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~          ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~          ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~          ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~          ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~          ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~          ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~          ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~          ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~          ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~          ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~          ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~          ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~          ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~          ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~          ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~          ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~          ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~          ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~          ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~          ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~          ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~          ;
+----------------+-------+------+-------------------+


+-------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add0 ;
+------------------------+-------------+----------------------------+
; Parameter Name         ; Value       ; Type                       ;
+------------------------+-------------+----------------------------+
; LPM_WIDTH              ; 32          ; Untyped                    ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                    ;
; LPM_DIRECTION          ; ADD         ; Untyped                    ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                    ;
; LPM_PIPELINE           ; 0           ; Untyped                    ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                    ;
; REGISTERED_AT_END      ; 0           ; Untyped                    ;
; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                    ;
; USE_CS_BUFFERS         ; 1           ; Untyped                    ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                    ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH         ;
; DEVICE_FAMILY          ; ACEX1K      ; Untyped                    ;
; USE_WYS                ; OFF         ; Untyped                    ;
; STYLE                  ; FAST        ; Untyped                    ;
; CBXI_PARAMETER         ; add_sub_5nh ; Untyped                    ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                 ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY               ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE               ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE             ;
+------------------------+-------------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Feb 25 04:49:40 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off control -c control
Info: Found 1 design units, including 1 entities, in source file control.v
    Info: Found entity 1: control
Info: Elaborating entity "control" for the top level hierarchy
Warning (10005): Verilog HDL or VHDL warning at control.v(21): can't check case statement for completeness because the case expression has too many possible states
Info: Found 1 design units, including 1 entities, in source file ../../../../quartus60/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0"
Info: Found 1 design units, including 1 entities, in source file ../../../../quartus60/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info: Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "32"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Found 1 design units, including 1 entities, in source file ../../../../quartus60/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder|a_csnbuffer:oflow_node", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info: Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "32"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info: Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "32"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Found 1 design units, including 1 entities, in source file ../../../../quartus60/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info: Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "32"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info: Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "32"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Duplicate registers merged to single register
    Info: Duplicate register "always0~39" merged to single register "always0~45"
    Info: Duplicate register "always0~41" merged to single register "always0~45"
    Info: Duplicate register "always0~43" merged to single register "always0~45"
    Info: Duplicate register "always0~31" merged to single register "always0~37"
    Info: Duplicate register "always0~33" merged to single register "always0~37"
    Info: Duplicate register "always0~35" merged to single register "always0~37"
    Info: Duplicate register "always0~23" merged to single register "always0~29"
    Info: Duplicate register "always0~25" merged to single register "always0~29"
    Info: Duplicate register "always0~27" merged to single register "always0~29"
    Info: Duplicate register "always0~15" merged to single register "always0~21"
    Info: Duplicate register "always0~17" merged to single register "always0~21"
    Info: Duplicate register "always0~19" merged to single register "always0~21"
    Info: Duplicate register "always0~7" merged to single register "always0~13"
    Info: Duplicate register "always0~9" merged to single register "always0~13"
    Info: Duplicate register "always0~11" merged to single register "always0~13"
    Info: Duplicate register "always0~0" merged to single register "always0~5"
    Info: Duplicate register "always0~1" merged to single register "always0~5"
    Info: Duplicate register "always0~3" merged to single register "always0~5"
Info: Implemented 164 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 24 output pins
    Info: Implemented 135 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Feb 25 04:49:43 2007
    Info: Elapsed time: 00:00:03


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in C:/altera/ym/text9/keyboard/control/control.map.smsg.