control.tan.summary

来自「一些很好的FPGA设计实例」· SUMMARY 代码 · 共 57 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 16.500 ns
From           : D[1]
To             : DATA[6]~reg0
From Clock     : --
To Clock       : en
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 9.600 ns
From           : always0~45
To             : DATA[0]
From Clock     : en
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 0.500 ns
From           : D[0]
To             : DATA[4]~reg0
From Clock     : --
To Clock       : en
Failed Paths   : 0

Type           : Clock Setup: 'en'
Slack          : N/A
Required Time  : None
Actual Time    : 47.39 MHz ( period = 21.100 ns )
From           : i[0]
To             : DATA[6]~reg0
From Clock     : en
To Clock       : en
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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