reg.tan.summary

一些很好的FPGA设计实例

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 8.400 ns
From           : E
To             : 74194:inst|38
From Clock     : --
To Clock       : H
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 9.400 ns
From           : 74194:inst|41
To             : QA
From Clock     : H
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -5.000 ns
From           : SR
To             : 74194:inst|41
From Clock     : --
To Clock       : H
Failed Paths   : 0

Type           : Clock Setup: 'H'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 200.00 MHz ( period = 5.000 ns )
From           : 74194:inst|39
To             : 74194:inst|40
From Clock     : H
To Clock       : H
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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