reg_latch.qws

来自「一些很好的FPGA设计实例」· QWS 代码 · 共 30 行

[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
ptn_Child2=Document-1
ptn_Child3=Document-2
ptn_Child4=Document-3
[ProjectWorkspace.Frames.ChildFrames.Document-0]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
DocPathName=Block1.bdf
DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde}
WindowPlacement=MCAAAAAAAAAAAAAABAAAAAAAPPPPPPPPPPPPPPPPMPPPPPPPEOPPPPPPIFAAAAAAMGAAAAAAFOCAAAAABIBAAAAA
IsActiveChildFrame=False
ptn_Child1=StateMap
[ProjectWorkspace.Frames.ChildFrames.Document-3]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-3.ViewFrame-0]
DocPathName=../../quartus60/win/pin_planner.ppl
DocumentCLSID={428be327-2a68-4a16-a2c9-0502a8811afc}
WindowPlacement=MCAAAAAAAAAAAAAABAAAAAAAPPPPPPPPPPPPPPPPMPPPPPPPEOPPPPPPAAAAAAAAAAAAAAAADHCAAAAAJBBAAAAA
IsActiveChildFrame=False
ptn_Child1=StateMap
[ProjectWorkspace.Frames.ChildFrames.Document-3.ViewFrame-0.StateMap]
AFC_CMP_AP_NAME=reg_latch
AFC_PROJ_DB_PATH=C:/altera/ym/text5/db/reg_latch.quartus_db
AFC_IN_REPORT=False