reg_latch.pin

一些很好的FPGA设计实例

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 -- functions, and any output files any of the foregoing 
 -- (including device programming or simulation files), and any 
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 -- Agreement, or other applicable license agreement, including, 
 -- without limitation, that your use is for the sole purpose of 
 -- programming logic devices manufactured by Altera and sold by 
 -- Altera or its authorized distributors.  Please refer to the 
 -- applicable agreement for further details.
 -- 
 -- This is a Quartus II output file. It is for reporting purposes only, and is
 -- not intended for use as a Quartus II input file. This file cannot be used
 -- to make Quartus II pin assignments - for instructions on how to make pin
 -- assignments, please see Quartus II help.
 ---------------------------------------------------------------------------------



 ---------------------------------------------------------------------------------
 -- NC            : No Connect. This pin has no internal connection to the device.
 -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (3.3V).
 -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
 --                 of its bank.
 -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
 --					It can also be used to report unused dedicated pins. The connection
 --					on the board for unused dedicated pins depends on whether this will
 --					be used in a future design. One example is device migration. When
 --					using device migration, refer to the device pin-tables. If it is a
 --					GND pin in the pin table or if it will not be used in a future design
 --					for another purpose the it MUST be connected to GND. If it is an unused
 --					dedicated pin, then it can be connected to a valid signal on the board
 --					(low, high, or toggling) if that signal is required for a different
 --					revision of the design.
 -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
 --					This pin should be connected to GND. It may also be connected  to a
 --					valid signal  on the board  (low, high, or toggling)  if that signal
 --					is required for a different revision of the design.
 -- GND*          : Unused  I/O  pin.   This pin can either be left unconnected or
 --           	    connected to GND.  Connecting this pin to GND will improve the
 --           	    device's immunity to noise.
 -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
 -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
 -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
 -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
 -- NON_MIGRATABLE: This pin cannot be migrated.
 ---------------------------------------------------------------------------------

Quartus II Version 6.0 Build 178 04/27/2006 SJ Full Version
CHIP  "reg_latch"  ASSIGNED TO AN: EPM7032AELC44-4

Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
-------------------------------------------------------------------------------------------------------------
CLRN                         : 1         : input  : LVTTL             :         :           : N              
GND+                         : 2         :        :                   :         :           :                
VCCINT                       : 3         : power  :                   : 3.3V    :           :                
1Q                           : 4         : output : LVTTL             :         :           : N              
2Q                           : 5         : output : LVTTL             :         :           : N              
3Q                           : 6         : output : LVTTL             :         :           : N              
TDI                          : 7         : input  : LVTTL             :         :           : N              
4Q                           : 8         : output : LVTTL             :         :           : N              
1QN                          : 9         : output : LVTTL             :         :           : N              
GND                          : 10        : gnd    :                   :         :           :                
2QN                          : 11        : output : LVTTL             :         :           : N              
3QN                          : 12        : output : LVTTL             :         :           : N              
TMS                          : 13        : input  : LVTTL             :         :           : N              
4QN                          : 14        : output : LVTTL             :         :           : N              
VCCIO                        : 15        : power  :                   : 3.3V    :           :                
3D                           : 16        : input  : LVTTL             :         :           : N              
GND*                         : 17        :        :                   :         :           :                
GND*                         : 18        :        :                   :         :           :                
GND*                         : 19        :        :                   :         :           :                
GND*                         : 20        :        :                   :         :           :                
4D                           : 21        : input  : LVTTL             :         :           : N              
GND                          : 22        : gnd    :                   :         :           :                
VCCINT                       : 23        : power  :                   : 3.3V    :           :                
1D                           : 24        : input  : LVTTL             :         :           : N              
GND*                         : 25        :        :                   :         :           :                
GND*                         : 26        :        :                   :         :           :                
GND*                         : 27        :        :                   :         :           :                
GND*                         : 28        :        :                   :         :           :                
GND*                         : 29        :        :                   :         :           :                
GND                          : 30        : gnd    :                   :         :           :                
GND*                         : 31        :        :                   :         :           :                
TCK                          : 32        : input  : LVTTL             :         :           : N              
GND*                         : 33        :        :                   :         :           :                
GND*                         : 34        :        :                   :         :           :                
VCCIO                        : 35        : power  :                   : 3.3V    :           :                
GND*                         : 36        :        :                   :         :           :                
GND*                         : 37        :        :                   :         :           :                
TDO                          : 38        : output : LVTTL             :         :           : N              
GND*                         : 39        :        :                   :         :           :                
GND*                         : 40        :        :                   :         :           :                
GND*                         : 41        :        :                   :         :           :                
GND                          : 42        : gnd    :                   :         :           :                
CLK                          : 43        : input  : LVTTL             :         :           : N              
2D                           : 44        : input  : LVTTL             :         :           : N